We have developed a methodology aimed at accurately determining the various forms of energy transfer (convective loss, radiative loss and absorption of lamp energy by the wafer)occurring in any advanced RTP system, based on basic system identification experiments and simple 3-dimensional physical model depicting the heat transfer processes. The identification experiments help in estimating the uncertain system dependent factors which characterize the various forms of energy transfer, which may be otherwise difficult to calculate on pure theoretical basis. This methodology forms the basic building block of our effort to develop a tool which can predict the temperature distribution across the wafer in a realistic way. This tool can be used both as a wafer temperature control algorithm in any advanced RTP system as well as by an end user who is equipped with a not so advanced, but multizone, RTP system( the one with the user defined power levels to various zones).

A Universal Thermal Module™ (UTM™) has been developed for vacuum-integrated cluster RTP and MOCVD as well as stand-alone atmospheric RTP applications. The UTM™ architecture provides highly modular RTP and MOCVD tool configurations for various single-wafer thermal processes. The UTM™ design comprises a temperature-controlled UHV-grade process chamber as well as an ultraclean gearless wafer rotation assembly for improved temperature uniformity and enhanced built-in reliability. The UTM™ RTP employs bottom/backside wafer heating using a multi-zone axisymmetric illuminator and a reflective multi-zone gas showerhead located above the wafer. Precision RTP control is achieved using a multi-zone controller in conjunction with a multipoint sensor system with real-time multi-zone compensations for wafer emissivity and illuminator light interference effects. The RTP temperature measurement and control techniques fully compensate for any axisymmetric or non-axisymmetric wafer emissivity patterns, eliminating the need for pre-RTP wafer backside conditioning. The UTM™ showerhead provides capabilities for ultraclean multi-zone gas injection and in-situ RF plasma for MOCVD and RTCVD processes. The UTM™ MOCVD module meets the most stringent specifications and tool parameters for various metallization and high-K dielectric deposition applications. This module has been used for deposition of low-resistivity copper films with excellent void-free sub-half-micron gap fill for high-performance multilevel interconnects. The UTM™ RTP and MOCVD modules have been implemented based on design optimizations in a virtual reactor environment.

This work presents the results of process development in a cluster tool designed for the gate stack process of cleaning, gate oxidation, and polysilicon chemical vapor deposition. The cluster tool connects three single wafer process chambers together with a vacuum transfer chamber. The purpose of this work was to test the feasibility of the single wafer processing gate oxidation cluster tool from an electrical performance standpoint, Cleaning was performed using a gas/vapor phase process, and the results using a standard oxide indicate that gas/vapor phase cleaning is at the least comperable and possibly more effective at contamination removal than the standard RCA wet cleaining process. The oxidation was performed using rapid thermal processing, and the effect of adding nitrogen to the oxide by oxidation in an N2O containing ambient was tested. The results indicated that oxides at least at good as those grown in a conventional furnace could be produced in the cluster tool, and the nitrogen at the oxide-substrate interface improves the reliability of the oxide if the nitrogen concentration is kept below 1 atomic %.

While repeatable and accurate measurement of temperature in rapid thermal processing (RTP) remains a subject of ongoing research, inception of large-diameter wafers and deep subhalf micron design rules may be viewed as good news for implementing RTP during the development phase for later transfer to volume manufacturing. To date, the only well-established application of RTP in manufacturing is silicide annealing. However, research during the past decade has demonstrated the feasibility of using RTP to replace essentially all furnace-based thermal processes in sub-half micron process flows. These developments in the RTP capability offer several technological and economic benefits such as improved defect control, higher product yields, and faster development cycles for DRAM-type technologies at a reduced cost and with an earlier entry of the driver products during the revenue-generating period.

In this paper, we review several applications of RTP such as silicide anneals, borophosphosilicate glass (BPSG) reflow, dopant activation, and rapid thermal nitridation (RTN) and discuss the integration issues related to advanced process flows. Furthermore, we highlight important manufacturing parameters like throughput, machine cost and uptime, software and hardware issues, wafer dimensional analysis, and simulation expectations. While considering volume manufacturing, we make some calibration and process control recommendations.

The diversity of semiconductor manufacturing as well as the decreasing thermal budget for ULSI devices has driven semiconductor equipment manufacturers to develop and improve thermal processing solutions. Recent advances include new temperature measurement systems for rapid thermal processors (RTP), the development of the small batch fast ramp furnace (SBFR), as well as improved capability and load size in the conventional vertical batch furnace (BF). This paper will review the RTP, SBFR, and batch furnace for typical atmospheric front end of the line applications. Throughput and cycle time will be modeled for each type of system. Sematech's cost of ownership model will be employed to evaluate the relative importance of throughput, mean time between failure, and equipment cost. And finally an overview discussion of the issues associated with temperature measurement and system configurations of the RTP will be given.

Thin film dielectrics have been prepared in a cluster processing system with chambers for plasma-assisted, rapid-thermal processing, and on-line Auger electron spectroscopy (AES). A low-thermal budget process for the formation of homogeneous silicon oxynitride (OXN) alloy films is presented. This Na2-based plasma-CVD process has (i) increased process latitude for the formation of N-rich alloys, and (ii) results in lower bonded-H concentrations, in comparison with a similar NH3-based process. Gate dielectric formation consists of (i) a 300°C plasma-assisted oxidation for removal of residual hydrocarbons, and formation of an Si-SiO2 interface protected by ∼0.5-0.6 nm of oxide, (ii) a 300°C plasma-assisted CVD of oxynitride films from N2O, N2, and SiH4, and (iii) a 30 s, 900°C post-deposition rapid-thermal anneal in an ambient that contains sufficient oxygen to prevent decomposition of the Si/SiO2 interface. On-line AES and off-line infrared (IR) spectroscopy have been used to characterize chemical bonding, showing that the deposited films are pseudo-binary alloys lying on a join-line from SiO2 and Si3N4 in a ternary composition diagram. Electrical characterization of MOS capacitors, consisting of O-OXN-O structures, using C-V techniques is discussed.

This paper reports on the formation of high quality ultrathin oxynitride gate dielectric by in-situ rapid thermal multiprocessing. Four such gate dielectrics are discussed here; (i) in-situ NO-annealed SiO2, (ii) N2O- or NO- or O2-grown bottom oxide/RTCVD SiO2/thermal oxide, (iii) N2O-grown bottom oxide/Si3N4/N2O-oxide (ONO) and (iv) N2O-grown bottom oxide/RTCVD SiO2/N2O-oxide. Results show that capacitors with NO-based oxynitride gate dielectrics, stacked oxynitride gate dielectrics with varying quality of bottom oxide (O2/N2O/NO), and the ONO structures show high endurance to interface degradation, low defect-density and high charge-to-breakdown compared to thermal oxide. The N2O-last reoxidation step used in the stacked dielectrics and ONO structures is seen to suppress charge trapping and interface state generation under Fowler-Nordheim injection. The stacked oxynitride gate dielectrics also show excellent MOSFET performance in terms of transconductance and mobility. While the current drivability and mobilities are found to be comparable to thermal oxide for N-channel MOSFET's, the hot-carrier immunity of N-channel MOSFET's with the N2O-oxide/CVD-SiO2/N2O-oxide gate dielectrics is found to be significantly enhanced over that of conventional thermal oxide.

The resultant physical and electrical characteristics of dielectric layers grown or annealed in nitric oxide are presented. The layers formed or modified in nitric oxide are thinner but generally superior in quality to those grown in nitrous or dry oxide. The indications are that dielectrics formed or annealed in nitric oxide are a viable alternative to other techniques of producing ultra thin (≤ 5nm) dielectrics.

In this paper a new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N2O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si-SiO2 interface than either N2O oxynitride or nitridation of SiO2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N2O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress

Ultrathin SiO2 dielectric layers of thickness less than 100Å on silicon substrates have been prepared by dry oxidation and rapid thermal nitirdation (RTN). In this study, X-ray photoelectron spectroscopy and surface charge spectroscopy had been applied to study the nitrogen distribution in the dielectric layers and the change in the interface state density (Dit) due to the nitrogen incorporation. It is found that most of the incorporated nitrogen is located near the dielectric/Si interface and the nitrogen content increases with the RTN temperature. For the electrical properties, we found that the Dit, after RTN slightly decreases and the breakdown field strength deduced from the dielectric surface potential was enhanced by the incorporation of nitrogen.

For both advanced MOS technologies (gate length ≤ 0.25.μm) and EEPROMs, the quality and reproducibility of thin dielectric films (≤ 6 nm) are essential. To obtain such dielectrics involves very precise control of the silicon surface preparation and gate oxide growth. Furthermore, research into such supplementary properties of oxide as improved SiO2/Si interface resistance to current injections or enhanced p+gate resistance to boron penetration in the channel may require nitridation treatment. Such a sequence of steps can be carried out under controled atmosphere using a cluster tool. This paper presents the preliminary results obtained in a single wafer cluster tool on i) the surface preparation under ozone of a silicon wafer immediately after diluted liquid HF treatment and ii) the nitridation of the 6 nm gate oxide under low temperature, low pressure gaseous NO. It is shown that the NO molecule can be successfully used in Rapid Thermal Processing (RTP) and allows gate oxides to be nitrided with properties at least equivalent to those obtained under N2O nitridation, but with a strikingly reduced thermal budget.

Crucial steps in solar cell processing such as emitter diffusion and surface oxide passivation have been carried out by rapid thermal processing (RTP). Rapid thermal diffusion (RTD) of boron into silicon from APCVD borosilicates has been studied. Rapid thermal oxidation (RTO) of the heavily B-doped surfaces of these shallow junctions (0.2 μm) has been studied in view of applicability of this technique in solar cell processing. These shallow diffusions have excellent lateral uniformity over large areas and have high surface concentrations depending on the APCVD deposition conditions and on RTP conditions. The surface passivating oxides resulting from the RTO are exceptionally thick in case of heavy boron diffused surfaces. RTO does not cause considerable drive-in of the diffused junction profiles. In the contrary, the thick RTO oxides considerably reduce the surface concentration, thereby reducing the heavy doping effects in the junctions, making them more suitable emitters for devices such as solar cells. p+nn+ solar cells have been fabricated on n-type CZ silicon wafers by RTD of boron followed by RTO. The cells result in conversion efficiencies as high as 16.2% The passivation effect of RTO oxides have been investigated by analysing RTO MOS capacitors and are compared to conventional furnace oxides.

This paper investigates conditions of low thermal budget N2O and NO oxidation with simultaneous accumulation of 0.5 to 1 at% nitrogen at the SiO2/Si interface of thin oxide layers. A nitrogen accumulation model is presented. It is concluded that the nitrogen accumulation should be realized with oxidizing conditions at the interface to silicon and it is proposed to control the NO partial pressure in reactor gas for the desired nitrogen amount at tolerable thermal budget.

Microwave afterglow plasma oxidation at a low temperature (600 °C ) and rapid thermal annealing (RTA) were combined to grow high quality ultra-thin dielectrics. This new approach has a low thermal budget. The mid-gap interface state density of oxides pretreated in N2O plasma was decreased to about 5×1010 cm−2eV−1 after rapid thermal annealing at 950 °C.It was found that RTA is very effective for relieving the oxide stress and reducing the interface state density. Nitrogen incorporated in oxides by the N2O plasma pretreatment of the Si surface helped to reduce the interface state density. Microstructures of ultra-thin oxide grown by microwave afterglow oxidation with or without RTA were revealed by extended-X-ray-absorption-finestructure (EXAFS) and X-ray photoelectron spectroscopy (XPS) analysis.

Rapid thermal chemical vapor deposition (RTCVD) has been investigated as an alternative to low pressure chemical vapor deposition (LPCVD) for formation of sidewall spacer dielectric. Silane (SiH 4 ) and tetraethylorthosilicate (TEOS) were chosen as the silicon gas sources in these studies. Reasonable deposition rates were obtained for RTCVD oxides, oxynitrides and nitrides for use in thin sidewall spacer application. Refractive index and etch rate measurements suggest that oxides deposited with a 2 % flow rate ratio of SiH 4 /N2O and annealed at 900 °C for 10 seconds produces films with excellent structural quality. Refractive index and wet etch rate both exhibit a linear dependence with the gas flow ratio. An increase in deposition pressure decreased the refractive index while increasing the etch rate. Oxide and oxynitride dielectrics formed using SiH 4 had a much superior step coverage over a wide range of aspect ratios than TEOS dielectrics. Dit and breakdown fields for oxides and oxynitrides with 3 atomic % nitrogen were comparable to that of thermal oxide indicating their good electrical quality. The results reported suggest that RTCVD sidewall spacers are a promising candidate for use in future MOSFET devices.

Device-quality epi material can be grown at temperatures ranging from 600 to 800°C in commercially available production reactors. The exceptionally steep transitions of Ge, B and, to a lesser extent, P, are characteristics of Si and strained SiGe epi growth from dichlorosilane and germane in hydrogen ambient at atmospheric or reduced pressure. Although the growth rates depend on the dopant gas flows at low temperatures, layer thickness and doping level control is excellent. Selective multilayer growth at reduced pressure seems a viable process and can be applied in e.g. HBT's.

In spite of the fact that a lot of the progress in low-temperature epitaxy has been made in lampheated reactors, it is argued that RTP is not needed for low-temperature epitaxy. This is in contrast to conventional (high-temperature) epitaxy where RTP is becoming indispensable. Real RTP, heating and cooling the wafer in just a couple of seconds, would improve the throughput of the present generation single wafer epi reactors tremendously and seems feasible.

Material and device challenges for Rapid Thermal Processing (RTP) of heterostructures are discussed, focusing on RTP-based epitaxy in the Si/Si1−xGex system. While RTP-based heteroepitaxy offers enhanced processing flexibility, it also poses significant challenges for temperature measurement and control. Several examples of Si/Si1−xGex device structures are discussed from the point of view of the sensitivity of device parameters to variations in layer thickness and composition. The measured growth kinetics for Si and Si1−xGex are then used to estimate growth temperature tolerances for these structures. Demanding applications are expected to require temperature control and uniformity to within 0.5°C.

Future research challenges include the fabrication of structures with monolayer thickness control using self-limited growth techniques. Atomic layer epitaxy (ALE) is a well-known example of such a growth technique. In ALE, the wafer is cyclically exposed to different reactants, to achieve layer-by-layer growth. An RTP-based atomic layer epitaxy process, and its application to the growth of CdTe films, is briefly discussed. The extension to Column IV alloys follows readily. The RTP-based process enables self-limited growth for precursor combinations for which isothermal ALE is not feasible.

Rapid thermal epitaxy (RTE) is studied for a variety of applications including transistors as well as optoelectronic devices. Two transistor applications are discussed here. First, the growth of n-type epitaxial layers over n+ buried layers for low power BiCMOS, and second, the growth and fabrication of charge injection transistors (CHINTs) from a multi-layer structure including strained Si1−xGex layers.

Scaled bipolar transistors for BiCMOS integrated circuits require low collector-substrate capacitance in order to minimize power consumption. The unintentional incorporation of dopant into a growing epitaxial layer, known as autodoping, can affect the ultimate lower limit of the collector-substrate capacitance. In this work, we studied the effects of epitaxial layer growth rate, arsenic buried layer implant dose, and pre-epitaxial bake temperature on autodoping using RTE. To begin, we experimented with the buried layer implant dose to check its affect on lateral autodoping. The amount of autodoping increased when the buried layer implant dose increased, confirming the source of the arsenic autodoping as the buried layer. Also, in contrast to data from conventional reactors, we found the peak interface concentration and integrated dose in regions adjacent to the buried layer to be linearly dependent on the growth rate (i.e. low growth rates trap less arsenic at the substrate/epi layer interface). Next, by adjusting the pre-bake temperature over a range from 800 to 1050°C without changing the growth conditions, we first observed a rise in autodoping with temperature to 950°C at which point the incorporated autodoping dose and peak concentration began to fall. Through simulation of the evaporated arsenic from the buried layer and data for arsenic desorption from the silicon surface, we explain this behavior. Finally, using the data gathered on the autodoping characteristics of RTE, we show a process using two growth rate steps and a low temperature pre-bake step which completely eliminates the lateral autodoping peak. Using this new growth process, epitaxial silicon films over arsenic doped buried layers for low power BiCMOS are possible.

Charge injection transistors and logic elements have been successfully implemented in a Si/Si0.7Ge0.3 heterostructure grown by RTE on a Si substrate. Shallow p+ source and drain ohmic contacts are obtained by a boron diffusion from a selectively deposited boron doped Ge layer. Room temperature operation of the charge injection transistor is demonstrated for the first time. High frequency measurements indicate a short circuit current gain cutoff frequency of 6 GHz.

The initial growth of polycrystalline silicon (Si) and germanium-silicon alloys (GexSi1−x) from SiH4 and GeH4, where x is in the range of 0-0.4, in an RTMP reactor has been investigated using an in situ monitoring technique called reflectometry. An inhibition time is found which, for poly-Si in the temperature range of 550–650°C decreases with increasing temperature and for poly-GexSi1−x in the temperature range of 500–625°C shows the same behavior. The effect of total pressure, ranging from 0.10–1.20 mbar, is even stronger: an increasing pressure sharply decreases the inhibition time. For a selective deposition a low SiH4 and GeH4 partial pressure seems favorable, while for a non-selective deposition of poly-GexSi1−x alloys on (gate) oxides (for Thin Film Transistor applications) a high pressure or a pressure pulse at the start of the deposition process can be used.

In this paper, a detailed study is presented for the growth kinetics of rapid thermal chemical vapor deposition (RTCVD) of nitrogen-doped polysilicon using silane and ammonia chemistry. It is found that nitrogen doping has reduced the surface roughness and grain size of the RTCVD polysilicon film. Both the deposition rate and the incubation time of film growth depend strongly on the ammonia to silane flow ratio. We have proposed a novel structure of NICER (Nitrogen Incorporation into CMOS Gate Electrode by in-situ RTCVD). High performance and highly reliable dual gate CMOS can be formed by combining rapid thermal oxidation (RTO) with RTCVD.