In this paper we present for the first time the use of the Si2H6/H2/Cl2 chemistry for selective silicon epitaxy in a rapid thermal CVD reactor. Depositions were carried out in an ultra-high vacuum rapid thermal chemical vapor deposition (UHV-RTCVD) system designed and constructed at North Carolina State University. Experiments were performed over a temperature range of 650°C to 850°C and over a pressure range of 22 to 25 mTorr using a flow rate 100 sccm of 10% Si2H6 in H2 and 0 to 10 sccm of Cl2. Deposited layer thicknesses were evaluated using a combination of interferometry and profilometry. Without Cl2 over the range of 650°C to 850°C, the growth rate is approximately constant at 160 nm/min. exhibiting a weak dependence on temperature. A clear advantage of Si2H6 is that high growth rates compatible with single wafer manufacturing can be obtained at very low pressures thus minimizing the introduction of contaminants by the process gases. With the addition of C12, the growth rate is suppressed at temperatures below 800°C, but, at 800°C and above, it is affected only slightly for Cl2 flow rates below 5 sccm. As the Cl2 flow rate is increased past 5 sccm, the growth rate at higher temperatures becomes a strong function of Si2H6:Cl2 ratio. Excellent selectivity with respect to patterned SiO2 and Si3N4 was obtained over the entire Cl2 flow rate range suggesting that even lower Cl levels may be sufficient for selective deposition. This implies that selectivity can be obtained with Si:Cl ratios much lower than those introduced by the more commonly used SiH2Cl2 chemistry. Furthermore, because Si2H6 can provide high growth rates at very low pressures, the total partial pressures of Cl2 and resulting chlorinated species can be significantly lower than typically required for selectivity. Our results indicate that C12 successfully enhances selectivity and yields highly selective depositions for process durations well within the practical limits of single wafer manufacturing.

Complete epitaxial Si-SiGe-Si- stacks with a defined doping profile for each component have been deposited on Si substrates from the system SiH4, GeH4, H2, B2H6, PH3 by RTCVD. The deposition has been carried out at a temperature of 650°C for Si and of 500°C for SiGe, respectively, both at a pressure of 2 mbar. The developed epitaxial process including an effective H2 in-situ preclean annealing has been integrated in a simple double mesa technology for the preparation of SiGe base heterojunction bipolar transistors (HBT). Despite the simplicity of the technology and the lithographical level allowing emitter dimensions of 2.3×2.5 μm2 only, test devices on 4” wafers reached transit frequencies fT and maximum oscillation frequencies fmax of higher than 60 GHz and 30 GHz, respectively. Besides, a low base current has been measýnl as proof for a good layer quality.

In this paper, we present an application of ultra high Vacuum Rapid Thermal Chemical Vapor Deposition (UHV-RTCVD) to MOSFET channel engineering. MOSFETs were fabricated on ultra-thin (200 Å), moderately doped (l×1017 - 6×1018 cm−3) p-type epitaxial layers selectively grown in active areas defined by standard LOCOS isolation. The selective epitaxy was achieved using a novel Si2H6Cl2/B2H6 process at 800°C and at a total pressure under 30 mtorr. Low thermal budget processing techniques were emphasized to minimize spread in the channel doping profile. Threshold voltages below 0.6 V were obtained. Transistors with effective channel lengths of 0.45 μm exhibit subthreshold slopes from 78 to 92 mV/decade determined by the epitaxial channel doping density. We have found that by using ultra-thin channels, expected transconductance degradation at high channel doping densities can be minimized. Furthermore, ultra-thin channels help reduce the sensitivity of the threshold voltage on substrate bias. The results show that low temperature selective silicon epitaxy can be used to form ultra-shallow channel doping profiles that can enhance the performance of MOSFETs in the deep submicron regime.

In this paper, we present alternative uses of rapid thermal chemical vapor deposition (RTCVD) in forming junctions for the raised source/drain MOSFET. The results will include applications of epitaxial silicon, SixGe1−x and TiSi2 all selectively deposited in dedicated coldwalled, lamp heated high or ultra high vacuum RTCVD reactors. Two general approaches will be considered : 1) ultra shallow junction formation in silicon followed by a selective deposition process to form a raised contact, 2) selective deposition to obtain a layer that can be used as a solid diffusion source and as a sacrificial layer for self-aligned silicide formation. In the first approach, junctions are formed typically by low energy ion-implantation. In this paper, we present rapid thermal vapor phase doping (RTVPD) as an alternative to ion-implantation to form defect free ultra-shallow junctions in Si. The method involves exposing a silicon wafer to a dopant gas (such as B2H6) at a moderate temperature (∼600°C) for a short time and subsequent annealing for drive-in. This is followed by either selective epitaxy and conventional self-aligned TiSi2 formation or selective deposition of a low-resistivity C54 TiSi2 from TiCl4 and SiH4. In the second approach, first, a semiconductor (Si, polysilicon or SixGe1−x) is deposited selectively. If the material is undoped, doping can be achieved by ion-implantation. In-situ doping is also possible as will be shown with p- and n-type SixGe1−x at temperatures as low as 625°C using B2H6 or PH3. The doped layer is then used as a solid diffusion source to form the junctions by out-diffusion. Using these different approaches, we present examples of high quality junctions in Si as shallow as a few hundred angstroms. The techniques are compared based upon their robustness, complexity, equipment and thermal budget requirements.

The rapid thermal annealing of doped (SOD) and undoped (SOG) glass films spinned onto silicon from diluted or undiluted solutions has been investigated. The dilution performed by methanol has allowed to obtain oxide films as thin as 10 nm.

The optical measurements of annealed SOG films have shown that good oxide films without oxygen deficiency are achievable. The electrical characteristics of Al-gate capacitors assessed by Capacitance-voltage measurements have shown a great dependence of the water content in the range of 600–850°C before reaching a typical dielectric constant value near 3.8 at higher temperatures. Low Interface state densities values obtained at temperature up to 900°C confirm the curing effect of a rapid thermal annealing.

On the other hand, we have demonstrated that the efficiency of rapid thermal diffusion from boron or phosphorus SOD films deposited on Si wafers depends on the source composition and its thickness. In particular, we have shown that it is possible to control the junction depth, the surface concentration and the minority-carrier diffusion length by varying the amount of dopant concentration in the solution, the thickness of the doped oxide film and the rapid thermal processing parameters. Futhermore, the remaining doped SOG film can play the role of an efficient oxide passivation layer.

Physical vapor deposition of Group VI elements (Cr, Mo, W) can lead to the formation of a metastable A-15 crystal structure under certain processing conditions. Typically, a thermally induced transformation of the metastable A-15 structure into the equilibrium body centered cubic structure has been accomplished by conventional furnace annealing at T/Tm ≈ 0.3 from tens of minutes to several hours. In this study we report on the use of rapid thermal annealing to transform sputter deposited A- 15 crystal structure tungsten and chromium thin films into body centered cubic films within the same temperature range but at times on the order of one minute. The minimum annealing times and temperatures required for complete transformation of the A-15 phase into the BCC phase varied from sample to sample, indicating that the transformation was dependent on the film characteristics. The electrical resistivity of A-15 Cr and W films was measured before and after rapid thermal annealing and was found to significantly decrease after transformation into the body center cubic phase.

The study evaluates the barrier integrity of Rapid Thermal Processed (RTP) titanium layer to form TiSi2/TiN and sputter deposited TiN layer annealed in RTP system. Various temperatures and ambient conditions were used during processing. Subsequent effects of the W-plug process on the TiN layer have been evaluated in terms of effects of WF6 on the underlying Ti/TiN layer.

Evaluation of the WF6 on the via side walls and the via corners will be the primary focus of this work. Results will be discussed in terms of effective TiN thickness the process of formation of TiN and its stability

β-FeSi2 is a semiconductor with a potential for photovoltaic and optoelectronic applications. The preparation of β-FeSi2-layers by rapid thermal processing (RTP) of Fe layers on silicon is investigated in this paper. Fe layers with typical thicknesses of 30 nm were sputtered on Si (100) substrates. We correlated the surface morphology of samples subjected to different RTP treatments with their composition and phase content. Phase transformations during the anneal were also studied by in-situ emissivity measurements. Rectifying and contacting behaviour of silicide/silicon heterojunctions prepared at several RTP-temperatures is presented at the end of this paper. Since it is not possible to prepare β-FeSi2-layers without a presence of either FeSi or α-FeSi2 metallic phases, these structures have poor heterojunction characteristics.

In this work, we have studied the formation of ultra-shallow p-type junctions by rapid vapor phase doping. The doping process was performed in an ultra high vacuum rapid thermal processing system using 0.1 l/min of a B2H6/H2 mixture. The B2H6 content of the mixture was only. 500 ppm corresponding to a B2H6 flow of 50 μl/min. In contrast, previous work in conventional and rapid thermal processing systems used B2H6 flows as high as 0.1 l/min which tend to form either pure boron or boron silicide layers depending on the processing conditions. In this study we exposed 4″, (100) oriented, n- and p-type silicon wafers to the B2H6/H2 mixture for varying growth conditions. Boron junction profiles were obtained at temperatures ranging from 650°C to 850°C. Boron dose, peak concentration, and junction depth were found as a function of growth temperature and time. Our results show that ultra-shallow (≤ 500 Å) boron profiles with surface concentrations above 1020 cm−3 can be obtained in Si at temperatures as low as 650°C. Typical process times range from 15 to 90 seconds making the process a good candidate for single wafer manufacturing in rapid thermal processing systems.

In this study, we have fabricated ultra-shallow p+n junctions by boron outdiffusion from selectively deposited Si epitaxial layers. The undoped layers (900 – 1000 Å) were selectively deposited on active areas in a UHV-RTCVD reactor using Si2H6 and Cl2 at 800°C and at a total pressure less than 30 mTorr. Junctions were formed by BF2 ion-implantation into epitaxial layers with and without Ge preamorphization followed by RTA at 1000°C and 1050°C for 10 s in Ar. Junction depths ranging from 400 Å to 700 Å were formed at a background concentration of l×1016 cm−3. Abrupt boron profiles with epitaxy/substrate interface concentrations on the order of 1020 cm-3 were formed. Self-aligned TiSi2 was formed at four different thicknesses by evaporating 100, 200, 300 or 400 Å thick Ti followed by a two-step RTA cycle with a selective etch between to remove the unreacted Ti on Si02. Our results show that raised junctions with a Ti thickness of 400 Å (corresponding to a TiSi2 thickness over 900 Å and consumption of the entire epitaxial layer) exhibit a reverse leakage of less than 10 pA for a device area of 800×800 μm2. This corresponds to areal and peripheral leakage current densities of 67 pA/cm2 and 4 pA/cm. Therefore, thick silicide layers can be used on raised junctions reducing the junction sheet resistance and eliminating the possibility of silicide agglomeration. Furthermore, implantation damage in substrate is eliminated by confining the implant into the raised region which is later consumed during silicide formation.

Rapid thermal annealing (RTA) of Fe-Si layers co-deposited on n- and p- type Si (100) and Si-capped relaxed Si0.6Ge0.4 (100) substrates was studied. Relaxed (100) Si0.6Ge0.4 epitaxial layers represent a pseudo-matched substrate for the β-FeSi2 phase. Fe-Si layers with a 1:2 composition ratio were deposited at room temperature in an MBE system. Samples were then subjected to a rapid thermal annealing in a H2/N2-atmosphere in the temperature range between 500 and 800 °C. Conversion electron Mössbauer spectroscopy showed that the layers consist of the β-FeSi2 phase. Nomarski microscopy revealed crystal grains of the diameter from 5 to 10 μm. Cross-section transmission electron microscopy study found smooth surfaces and interfaces. No significant structural defects were found inside the grains. Differences between current-voltage characteristics of simple devices prepared on these layers agree with the trends expected from their band diagrams.

Local motion, diffusion and interaction of impurities in solids are important aspects of semiconductor material and device processing. Rapid thermal processing (RTP) is extremely concerned and appears to offer significant advantages in these areas. As oxygen is one of the dominant impurities present in silicon, various applications require different level of oxygen to improve the device performance.

In this work, we have taken the advantage of this feature to study the effects of the oxygen concentration in silicon on the rapid thermal co-diffusion of phosphorus and aluminium. In particular, we will show that the large enhancement of the minority carrier diffusion length (LD) due to this process can be related to the presence of oxygen and carbon which influences during the thermal cycle are of importance.

The effects of N2, O2, and Ar gas RTA treatments on Ti, TiN, and Ti-polycide film characteristics have been investigated in anticipation of the trend in DRAM development toward lower resistance materials to replace the standard WSi2, WSi2 on doped polycrystalline silicon (W-polycide), and doped polysilicon conductors used in interconnections, transistor gates, and contact-hole plugs, respectively. The reactivities of Ti and TiN in N2 and O2 gases are markedly different. Film characteristics such as sheet resistance, crystallinity, and elemental composition remain unchanged for TiN RTA-treated in N2 but vary significantly for Ti. In the case of Ti, XRD and XPS data indicate the formation of intermediate Ti-rich TiN or Ti2N compounds prior to the final TiN phase. Similarly, RTO-treated TiN shows a slower oxide growth rate compared with that of Ti. In the case of TiN, a surface layer of rutile phase TiO2 is directly formed, whereas for Ti the data suggest the formation of Ti-rich oxides such as Ti2O or TiO prior to the final TiO2 rutile phase. RTA treatment in different ambient gases can be used to create multilayer Ti-polycide and TiN/Ti metallization with self-aligned TiO2 passivation and etch-stop layers. TiN can also be applied with other materials and processes to form new DRAM memory cell capacitor structures.

For III-V device operation at 300 °C or above ohmic contacts have to consist of multilayered systems comprising an amorphous diffusion barrier. The contact system Au/Pt/Ti/WSiN/ Au/Ge/Ni-n-GaAs (n ≈ 5.1017 cm−3) has been developed and optimized with respect to the parameters of the barrier as well as the internal Au/Ge/Ni layers. The WSiN layer was deposited via reactive dc magnetron sputtering, the other layers by electron beam evaporation without breaking the vacuum. Annealing has been performed in a halogen lamp furnace. The contact resistance Rc as determined by TLM structures was measured as function of the annealing temperature and time. It was found that short-time annealings lead to a broad Rc minimum at 0.1 ωmm. For such Rc's the Au/Ge/Ni layer thicknesses must be ≥ 20/10/6 nm. Extended microstructural analysis was accomplished by XTEM/EDS and by AES and SNMS depth profiling. The typical alloying depth of the contact in the GaAs has been found to be about 50 nm, i.e. smaller than for the conventional Au/Ni/AuGe contact. The secondary phases formed (Au(Ga), NiGe(As)) are similar. With annealing conditions producing the desired Rc value, both Au(Ga) and NiGe(As) were observed in a bamboo-like arrangement at the metal-semiconductor interface. Degradation of Rc could be attributed to burying of the nickel-rich phases beneath gold-rich phases. This contact system is stable up to ≈ 300°C.

The silicidation of chemical vapor deposited (CVD) titanium has been investigated utilizing the Materials Research Corporation (MRC) PHOENIX™ cluster-tool platform which incorporated an AST elektronik GmbH cluster RTP chamber. This initial investigation focuses on C49 and C54 TiSi2 phase formation on bare silicon wafers. Equipment description, process results, comparison to classical PVD Ti silicide processing and future investigations will be presented.

Downscaling of microelectronics devices into the deep submicron regime requires ultrashallow junctions with reliable, low-resistivity contacts. The conventional self-aligned TiSi2 technology exhibits a serious limitation in forming contacts to ultra-shallow junctions due to silicon substrate consumption. Selective chemical vapor deposition of TiSi2 is being investigated because of its potential for overcoming this difficulty. In this process Si and Ti are supplied from the gas phase. The standard source gas for Ti has been TiCl4 while several gases including SiH4, Si2H6 and SiH2Cl2 are available for Si. The reports on this process indicate that optimized process conditions can deliver TiSi2 films without substrate consumption. Although this promise is significant, the deposition has a complicated chemistry involving processes such as silicon etching, silicon consumption or silicon pedestal deposition taking place along with TiSi2 deposition. Although, suppression of Si-substrate etching by excess H2 has been reported previously, a broad quantitative analysis has been lacking up until this reporting. In this work, we have examined silicon etching trends as a function of temperature for different H2:TiCl4 flow ratios using thermodynamic equilibrium calculations. We have also performed experiments in a lamp heated rapid thermal chemical vapor deposition reactor to study substrate etching over the temperature range of 600°C to 800°C and for H2 flows from 0 to 1000 sccm. A silicon conversion efficiency is defined as a measure of the amount of Si converted to TiSi2 relative to total Si used from the substrate and it is evaluated via both thermodynamic calculations and experiments with good agreement between the two. Our calculations suggest that at high temperatures, etching occurs mainly via formation of SiCl2. Addition of H2 into the reaction chemistry encourages formation of HCl reducing the amount of Cl available for SiCl2 formation responsible for substrate etching. Our results show that by optimizing the H2 flow rate and the process temperature silicon substrate etching can be effectively suppressed.