In this work, a possibility to further suppress silicon vapor condensation and formation of Si clusters in order to improve the growth rate and morphology during the low-temperature halo-carbon epitaxial growth of 4H-SiC was investigated. While a pronounced dissociating of Si clusters was clearly demonstrated, the enhancement of the growth rate and morphology was less significant then expected. In addition, the homogeneity of the growth rate and doping along the gas flow direction indicated that a significant and non-equal depletion of Si and C growth species takes place at sufficiently high HCl supply. HCl flow-dependent formation of polycrystalline Si and SiC deposits in the upstream portion of the hot zone was shown to be the source of this depletion.

We present theoretical calculations for the effect of spontaneous and piezoelectric polarization on the base resistance and frequency response of wurtzite Aluminium Gallium Nitride / Silicon Carbide Heterojunction Bipolar Transistors. Heterojunction Bipolar Transistors ( HBTs ) built using wide band gap semiconductors with AlGaN emitter and SiC base/collector hold the promise of high-power and high-frequency operation due to lower impact ionization coefficients and higher breakdown voltages. Further, Silicon Carbide has an indirect bang gap, and a large lifetime of minority carriers compared to most other compound semiconductors, which tend to have direct band gaps. This reduces the base recombination factor when the base is made from SiC, and helps to achieve higher overall current gain. Spontaneous and piezoelectric polarizations of the order of 1013 electrons per cm2 exist in wurtzite wide band-gap semiconductors. This has a non-trivial effect on band profile, charge transport and overall device characteristics since the polarization-induced charges are of the same order of magnitude as the total dopant charge content of critical device layers, and can significantly affect the amount of mobile charge depletion or accumulation in these layers. We calculate the effect of this polarization for both very thin pseudomorphic emitters and for relaxed emitter structures. We present calculations for the cases of Si-face and C-face SiC, since the signs of polarization-induced charges are different for the two cases. The intrinsic base resistance near emitter flat-band conditions is changed by a factor of 10 depending on the alloy composition of the emitter and the polarity of growth. The maximum frequency of oscillation under emitter flat-band conditions can also be modulated by the polarization-induced charges by up to 60%. Our calculations show that the technologically less prevalent C-face SiC can give a higher advantage for frequency response, especially when the emitter thickness is larger than the critical thickness.

Tight control of defects is pivotal for semiconductor technology. However, even the basic defects are not entirely understood in silicon carbide. In the recent years significant advances have been reached in identification of defects by combining the experimental tools like electron paramagnetic resonance and photoluminescence with ab initio calculations. We summarize these results and their consequences in silicon carbide based technology. We show recent methodological developments making possible the accurate calculation of absorption and emission signals of defects.

An effect of the nitrogen concentration on the concentrations of deep-level defects in bulk 6H-SiC single crystals is investigated. Six electron traps labeled as T1A, T1B, T2, T3, T4 and T5 with activation energies of 0.34, 0.40, 0.64, 0.67, 0.69, and 1.53 eV, respectively, were revealed. The traps T1A (0.34 eV) and T1B (0.40 eV), observed in the samples with the nitrogen concentration ranging from ∼2×1017 to 5×1017 cm−3, are attributed to complexes formed by carbon vacancies located at various lattice sites and carbon antisites. The concentrations of traps T2 (0.64 eV) and T3 (0.67 eV) have been found to rise from ∼5×1015 to ∼1×1017 cm−3 with increasing the nitrogen concentration from ∼2×1017 to ∼2.0×1018 cm−3. These traps are assigned to complexes involving silicon vacancies occupying hexagonal and quasi-cubic sites, respectively, and nitrogen atoms. The trap T4 (0.69 eV) concentration also substantially rises with increasing the nitrogen concentration and it is likely to be related to complexes formed by carbon antisites and nitrogen atoms. The midgap trap T5 (1.53 eV) is presumably associated with vanadium contamination. The presented results show that doping with nitrogen involves a significant change in the defect structure of 6H-SiC single crystals.

SiC films were deposited on Si substrate by low pressure hot-wall CVD using C3H8 (5% in H2)-SiH4 (2.5% in H2)-H2 gas system at 1270°C and 1370°C. In this paper, we compare the electrical characteristics of MOS capacitors fabricated on the 3C-SiC films grown at high and low temperatures, 1370°C and 1270°C, respectively. Although the cross-sectional TEM images indicate similar micro-structural quality of the SiC/Si interface for both temperatures, a quicker elimination rate of stacking faults with increasing thickness was observed in the films grown at 1370°C. Rocking curves from XRD measurements also indicate better crystallinity of the films grown at 1370°C. On the other hand, atomic force microscopy shows that the average surface roughness reduces with the reduction in growth temperature. MOS capacitors were made on films grown at both temperatures and characterized by high-frequency capacitance-voltage (HFCV), conductance-voltage (G-V), and current-voltage (I-V) measurements at room temperature. The MOS capacitors fabricated on both films exhibit good and almost identical C-V characteristics. Measurements of current-voltage characteristics in accumulation region showed smaller leakage for the film deposited at 1270°C. It is concluded that the decrease of the deposition temperature from 1370°C to 1270°C does not bring any remarkable negative impact on the interface properties of fabricated MOS capacitors.

Epitaxial growth on 3-in, 2° off-axis 4H SiC substrates has been conducted in a horizontal hot-wall CVD reactor with HCl addition. The thickness of the epiwafers ranges from 3m to 11 m and the growth rate is 7 − 7.5 m/h. Although a rougher surface and a higher triangular defect density is observed using the standard process for 4° growth, an improved process has resulted in reduced triangular defect density down to around 4 cm−2 and a smoother surface with the roughness of 1.1 nm for a 3.7 m thick epiwafer. Most interestingly, the basal plane dislocation density in the 2° off-axis epiwafers has been reduced to "negligible" levels, as confirmed by both the non-destructive UVPL mapping technique and the molten KOH etching on 2° epiwafers with thickness of around 10 m.

In this paper, we investigate the effective inversion layer mobility of lateral 4H-SiC MOSFETs. Initially, lateral n-channel MOSFETs were fabricated to determine the effect of p-type epi-regrowth on a highly doped p-well surface. The negative effects of the high p-well doping are still seen with 1500 Å p-type regrowth, while growing 0.5 um or more appears to be sufficient to grow out of the damaged area. A second experiment was performed to examine the effects of doping during epitaxial regrowth versus using ion implantation after regrowth. Comparable mobilities and threshold voltages were observed for equivalent epitaxial and implanted doping concentrations.

Three paramagnetic defects were revealed in amorphous hydrogenated carbon-rich silicon-carbon alloy films (a-SiC:H), which were attributed to the to silicon (Si) dangling bonds (Si DB), carbon-related defects (CRD), and bulk Si DB defect bonded with nitrogen atoms Si-N2Si. The effect of thermal annealing on a-SiC:H films was studied. It was established that annealing at high temperatures leads to formation of graphite-like carbon clusters in a-SiC:H films and strong increase of the concentration of CRD, while EPR signal from Si DB disappeared. A dependence of the resonance positions for both Si DB and CRD signals on the orientation of the magnetic field relative to the a-SiC:H film plane was found at Q-band and D-band frequencies and was explained by the influence of demagnetizing fields, which is becoming significant at high spin density of the paramagnetic centers, higher microwave frequency, and low temperature. A demagnetizing field of 11 Gs was found in annealed a-SiC:H film at 140 GHz and 4.2 K.

Synchrotron x-ray topographs taken using basal plane reflections indicate that the electron-hole recombination activated Shockley partial dislocations in 4H silicon carbide bipolar devices appear as either white stripes with dark contrast bands at both edges or dark lines. In situ electroluminescence observations indicated that the mobile partial dislocations correspond to the white stripes in synchrotron x-ray topographs, while immobile partial dislocations correspond to the dark lines. Computer simulation based on ray-tracing principle indicates that the contrast variation of the partial dislocations in x-ray topography is determined by the position of the extra atomic half planes associated with the partial dislocations lying along their Peierls valley directions. The chemical structure of the Shockley partial dislocations can be subsequently determined unambiguously and non-destructively.

Formation of interfacial dislocations (IDs) and dislocation half-loop arrays (HLAs) and their appearance in 4H-SiC epi-wafers are investigated by X-ray topography and KOH etching analysis. Synchrotron reflection X-ray topography demonstrates the ability to image IDs and HLAs simultaneously and reveal their densities as well as spatial distributions in the epi-wafers. The vertical location of IDs in the epi-wafer is also examined by this technique. The influence of wafer warp, in-situ H2 etching prior to epitaxial growth, substrate off-angle as well as the growth face (Si-face and C-face) on the densities and spatial distributions of IDs and HLAs are discussed.

We introduce defects into (1120) oriented highly N-doped 4H-SiC by surface scratching, bending and annealing in the brittle regime. Emerging defects at the sample surface are revealed by chemical etching of the deformed samples. The etch patterns are constituted of straight bulges and grooves exhibiting various topographical features. These etch figures correspond to the emergence of double stacking faults dragged by a pair of partial dislocations. In this paper, we discuss the links between the etch figure characteristics and the defect nature. Results obtained by optical and atomic force microscopy are completed by structural analysis of defects performed by transmission electron microscopy. Mobility of partial dislocations in 4H-SiC is discussed and correlated to their core composition and to the effect of the applied mechanical stress.

We have performed bias-stress induced threshold-voltage instability measurements on fully processed 4-H SiC power DMOSFETs as a function of bias-stress time, field, and temperature and have observed similar instabilities to those previously reported for lateral SiC MOSFET test structures. This effect is likely due to electrons tunneling into and out of near-interfacial oxide traps that extend spatially into the gate oxide. As long as the threshold voltage is set high enough to preclude the onset of subthreshold drain leakage current in the blocking state, then the primary effect of this instability is to increase the on-state resistance. For well-behaved power DMOSFETs, this would increase the power loss by no more than a few percent.

Epitaxial growth on Si-face nominally on-axis 4H-SiC substrates has been performed using horizontal Hot-wall chemical vapor deposition system. The formation of 3C inclusions is one of the main problem with growth on on-axis Si-face substrates. In situ surface preparation, starting growth parameters and growth temperature are found to play a vital role in the epilayer polytype stability. High quality epilayers with 100% 4H-SiC were obtained on full 2″ substrates. Different optical and structural techniques were used to characterize the material and to understand the growth mechanisms. It was found that the replication of the basal plane dislocation from the substrate into the epilayer can be eliminated through growth on on-axis substrates. Also, no other kind of structural defects were found in the grown epilayers. These layers have also been processed for simple PiN structures to observe any bipolar degradation. More than 70% of the diodes showed no forward voltage drift during 30 min operation at 100 A/cm2.

Fabrication procedure for silicon carbide power metal oxide semiconductor field effect transistors can be improved through simultaneous formation of ohmic contacts on both the n-source and p-well regions. We have succeeded in the simultaneous formation of Ni/Al ohmic contacts to n- and p-type SiC after annealing at 1000°C for 5 mins in an ultra-high vacuum. Ohmic contacts to n-type SiC were found when Al-layer thickness was less than about 5 nm while ohmic contacts to p-type SiC were observed for an Al-layer thickness greater than about 5 nm. Only the contacts with Al-layer thicknesses in the range of 5 to 6 nm exhibited ohmic behavior to both n- and p-type SiC, with specific contact resistances of 1.8 × 10−4 Ωcm2 and 1.2 × 10−2 Ωcm2 for n- and p-type SiC, respectively. An about 100 nm-thick contact layer was uniformly formed on the SiC substrate and polycrystalline δ-Ni2Si(Al) grains were formed at the contact/SiC interface. The distribution in values for the Al/Ni ratio in the δ-Ni2Si(Al) grains which exhibited ohmic behavior to both n- and p-type SiC was the largest. The smallest average δ-Ni2Si(Al) grain size was also observed in these contacts. Thus, the large distribution in the Al/Ni ratios and a fine microstructure were found to be characteristic of the ohmic contacts to both n- and p-type SiC.

This paper reports the influence of screw dislocations on the lateral/vertical growth behavior of chemical vapor deposited (CVD) on-axis homoepitaxial 4H-SiC films grown on patterned mesas. Electron channeling contrast imaging (ECCI) was utilized to image both atomic steps and dislocations while the film structure/orientation was determined using electron backscatter diffraction (EBSD). The presence and position of screw dislocations within the mesa impacted the resultant film thickness, lateral shape, and atomic step morphology. Mesa side walls that incline inwards due to faceting during screw-dislocation driven vertical film growth can intersect with the dislocation step sources near the side walls. If this occurs for all screw dislocations on a mesa, we observe a transition towards laterally dominated growth that produces webbed structures and films surfaces exhibiting significantly lower step densities. Transition from vertical to lateral dominated growth is consistent with ECCI imaged dislocation very near a mesa side wall.

SiC single crystal wafers grown by sublimation exhibit relatively high dislocation densities. While it is generally known that the overall dislocation density tends to decrease throughout crystal growth, there has been a limited quantitative analysis of such trend. In this study, we measured the density of threading dislocations in the wafers sliced from several SiC boules. Although the dislocation density in the wafers sliced from different boules could differ by orders of magnitude, a consistent empirical relationship was found between the dislocation density (ρ) and the axial wafer position within the crystal (w): ρ is proportional to w(−0.5).

Monte Carlo simulations were performed based on two assumptions: (i) during growth the threading dislocations move randomly in the lateral directions, and (ii) two dislocations of opposite sign annihilate when they come within a critical distance between them. Good agreement was achieved between the model and experimental results. The critical distance determined from the simulations was in the range between a few hundred Ă and a micron.

In practical use of the SiC power MOSFETs, further reduction of the channel resistance, high stability under harsh environments, and also, high product yield of large area devices are indispensable. Pn diodes with large chip area have been already reported with high fabrication yield, however, there is few reports in terms of the power MOSFETs. To clarify the difference between the simple pn diodes and power MOSFETs, we have fabricated four pn-type junction TEGs having the different structural features. Those pn junctions are close to the similar structure of DIMOS (Double-implanted MOS) step-by-step from the simple pn diodes. We have surveyed the V-I characteristics dependence on each structural features over the 2inch wafer. Before their fabrication, we formed grid patterns with numbering over the 2inch wafer, then performed the synchrotron x-ray topography observation. This enables the direct comparison the electrical and spectrographic characteristics of each pn junctions with the fingerprints of defects.Four structural features from TypeA to TypeD are as follows. TypeA is the most simple structure as same as the standard pn diodes formed by Al+ ion implantation (I/I), except that the Al+ I/I condition conforms to that of the p-well I/I in the DIMOS. The JTE structure was used for the edge termination on all junctions. While the TypeA consists of one p-type region, TypeB and TypeC consists of a lot of p-wells. The difference of Type B and C is a difference of the oxide between the adjacent p-wells. The oxide of TypeB consists of the thick field oxide, while that of TypeC consists of the thermal oxide corresponding to the gate oxide in the DIMOS. In the TypeD structure, n+ region corresponding to the source in the DIMOS was added by the P+ I/I. The TypeD is the same structure of the DIMOS, except that the gate and source contacts are shorted. The V-I measurements of the pn junctions are performed using the KEITHLEY 237 voltage source meters with semi-auto probe machine. An active area of the fabricated pn junctions TEGs are 150um2 and 1mm2. Concentration and thickness of the drift layer are 1e16cm−3 and 10um, respectively.In order to compare the V-I characteristics of fabricated pn junctions with their defects information that obtained from x-ray topography measurements directly, the grid patterns are formed before the fabrication. The grid patterns were formed over the 2inch wafer by the SiC etching. The synchrotron x-ray topography measurements are carried out at the Beam-Line 15C in Photon-Factory in High-Energy-Accelerator-Research-Organization. Three diffraction conditions, g=11-28, -1-128, and 1-108, are chosen in grazing-incidence geometry (improved Berg-Barrett method).In the presentation, the V-I characteristics mapping on the 2inch wafer for each pn junctions, and the comparison of V-I characteristics with x-ray topography will be reported.

The performance of SiC microwave power transistors is studied in fabricated class-AB power amplifiers and class-C switching power amplifier using physical structure of an enhanced version of previously fabricated and tested SiC MESFET. The results for pulse input in class-C at 1 GHz are; efficiency of 71.4 %, power density of 1.0 W/mm. The switching loss was 0.424 W/mm. The results for two class-AB power amplifiers are; the 30-100 MHz amplifier showed 45.6 dBm (∼ 36 W) output powers at P1dB, at 50 MHz. The power added efficiency (PAE) is 48 % together with 21 dB of power gain. The maximum output power at P1dB at 60 V drain bias and Vg= -8.5 V was 46.7 dBm (∼47 W). The typical results obtained in 200-500 MHz amplifier are; at 60 V drain bias the P1dB is 43.85 dBm (24 W) except at 300 MHz where only 41.8 dBm was obtained. The maximum out put power was 44.15 dBm (26 W) at 500 MHz corresponding to a power density of 5.2 W/mm. The PAE @ P1dB [%] at 500 MHz is 66 %.

Hole dominated avalanche multiplication and thus breakdown characteristics of ion implanted 4H-SiC p+-n−-n+ photodiodes were determined by means of photomultiplication measurements using 325 nm UV light. All the tested diodes exhibited low reverse leakage current and reasonably uniform avalanche breakdown. With avalanche widths of 0.2 µm to 1.5 µm and the capability to measure multiplication factor as low as 1.001, the room temperature impact ionization coefficients were precisely deduced from these 4H-SiC diodes using a local ionization model for electric fields ranging from 1.25 MV/cm to 2.8 MV/cm. The results agree with those reported by Ng et al. and are within the accuracy of both the C-V measurements and electric-field determinations.

In this paper, we present results of epitaxial layer deposition for production needs using our hot-wall CVD multi-wafer system VP2000HW from Epigress with a capability of processing 6×100mm wafers per run. Intra-wafer and wafer-to-wafer homogeneities of doping and thickness for full-loaded 6×100mm runs will be shown and compared to results of the former 7×3″ setup. The characteristic of the run-to-run reproducibility for the 6×100mm setup will be discussed. To demonstrate the suitability of the reactor for device production results on Schottky Barrier Diodes (SBD) processed in the multi-wafer system will be given. Furthermore, we show results for n- and p-type SiC homoepitaxial growth on 3″, 4° off-oriented substrates using a single-wafer hot-wall reactor VP508GFR from Epigress for the development of PiN-diodes with blocking voltages above 6.5 kV. Characteristics of n- and p-type epilayers and doping memory effects are discussed. 6.5 kV PiN-diodes were fabricated and electrically characterized. Results on reverse blocking behaviour, forward characteristics and drift stability will be presented.