We investigated the electronic levels of defects introduced in 4H-SiC α-particle detectors by irradiation with 1 MeV neutrons up to a fluence equal to 8x1015 n/cm2. As well, we investigated their effect on the detector radiation hardness. This study was carried out by deep level transient spectroscopy (DLTS) and photo-induced current transient spectroscopy (PICTS). As the irradiation level approaches fluences in the order of 1015 n/cm2, the material behaves as highly resistive due to a very great compensation effect but the diodes are still able to detect with a acceptably good charge collection efficiency (CCE) equal to 80%. By further increasing fluence, CCE decreases reaching the value of ≈ 20% at fluence of 8x1015 n/cm2.

The dominant peaks in the PICTS spectra occur in the temperature range [400, 700] K. Enthalpy, capture cross-section and order of magnitude of the density of such deep levels were calculated. In the above said temperature range the deep levels associated to the radiation induced defects play the key role in the degradation of the CCE. Two deep levels at Et = 1.18 eV and Et = 1.50 eV are likely to be responsible of such dramatic decrease of the charge collection efficiency. These levels were reasonably associated to an elementary defect involving a carbon vacancy and to a defect complex involving a carbon and a silicon vacancy, respectively.

The development of high power, high efficiency silicon carbide RF MESFETs is reported. High power densities of over 3W/mm have been measured for devices with total power output in excess of 25W. The devices have been fabricated using a novel lateral epitaxy technique. The MESFET employs a buried p-type depletion stopper in order to suppress short channel effects and increase the operation voltage. The use of the depletion stopper also allows high RF signal gain, while maintaining high voltage operation capability. Single-cell components measured on-wafer demonstrate an Ft of 10 GHz and a high unilateral gain.

Packaged 6-mm RF transistors have been evaluated using amplifier circuits designed for operation in classes A, AB or C. Operation in class AB demonstrated a saturated power of 20 W and a P1dB of 15W with a linear gain of over 16 dB at Vdd of 60 V for 2.25 GHz operation. Maximum drain efficiency is 56% for class AB operation, 48% at 1 dB compression point and 72% for class C at 2.25 GHz.

The forefront of semiconductor silicon carbide technology now approaches commercialization for both materials and device technology. The commercialization of SiC epitaxy processes requires improvement in defect density, uniformity and repeatability. Especially problematic are graphite particles, gas phase nucleation of particles and the limitations placed on achieving growth rates that can positively impact process costs. When it approached the same historical point of development, silicon epitaxy technology shifted to the use of chlorosilane precursor gases to suppress gas phase nucleation and achieve targeted growth rates. Recent work on SiC epitaxy chemistry now investigates the use of HCl, halocarbons and most recently chlorosilane precursors. This paper will review the original work on gas phase nucleation and its control in silicon epitaxy processes using HCl additives and chlorosilanes. Using established dissociation pathways for chlorosilanes, equilibrium chemical reaction models are used to assess the impact of HCl, halocarbons and chlorosilane precursors on growth rates and particle formation SiC epitaxy. Experimental data is presented on the comparative performance of HCl additive and chlorosilane precursors in SiC epitaxy and film properties.

Silicon carbide is a promising semiconductor material for electrical and optoelectronic applications in the area of high power, high temperature, high frequency and intense radiation. Many groups have worked on growing SiC bulk crystals by sublimation from SiC powder source at a temperature above 2000 oC under an argon environment. They have also worked on improving the crystal growth rate. Traditional approach is to increase furnace temperature to enhance the growth rate. However, high cost of inert crucible at high temperature and impurity caused by crucible degradation set limit on the maximum growth rate which can be achieved. Current existing crucible and other components in the furnace are no longer passive at high temperature. Also understanding of vapor transport during powder sublimation and the interplay between vapor transport and powder sublimation is important for the optimization of the sublimation growth process. A comprehensive numerical model combining heat transfer, sublimation, species transport, and powder porosity evolution of SiC sublimation growth process is developed in this paper. The mechanism of vapor transport is described, in which a driving force is introduced to explain vapor transport. A new method to increase crystal growth rate is proposed based on the model. The new method includes changing the initial powder porosity and creating a hole in the packed powder. Simulation results for the case with a central hole and without hole are presented. The results show that the powder sublimation rate increases by creating a hole, and it is also validated by experiments. The results also reveal that the mass of the as-grown crystal increases if the powder sublimation rate increases. Finally, the powder geometry is optimized using numerical simulations.

Electron paramagnetic resonance was used to study defects in high-purity semi-insulating (HPSI) substrates grown by high-temperature chemical vapor deposition and physical vapor transport. Deep level defects associated to different thermal activation energies of the resistivity ranging from ~0.6 eV to ~1.6 eV in HPSI substrates are identified and their roles in carrier compensation processes are discussed. Based on the results obtained in HPSI materials, we discuss the carrier compensation processes in vanadium-doped SI SiC substrates and different activation energies in the material.

Modeling and simulation of the SiC growth processes, Physical Vapor Transport (PVT), Chemical Vapor Deposition (CVD) and hybrid techniques, are sufficiently mature to be used as a training tool for engineers as well as a growth machine design tool, e.g. when building new process equipment or up-scaling old ones. It is possible (i) to simulate accurately temperature and deposition distributions, as well as doping (ii) to quantify the limiting phenomena, (iii) to understand the important role of different precursors in CVD and hydrogen additions in PVT. The first conclusion of this paper is the importance of the "effective" C/Si ratio during CVD epitaxy in hot-wall reactors and its capability to explain the doping concentrations. The second conclusion is the influence of the C/Si ratio in alternative bulk growth technique involving gas additions. Preliminary results show that fine tuning of H2 or precursor additions allow a better control of concentrations of residual and intentional doping.

In this paper we report the first 4H-SiC CMOS inverter, which was designed to be integrated in the process flow of a 4H-SiC power DMOSFET. The channels of both of the n channel and p-channel MOSFETs of the inverter were 50 um wide by 3 um long. NMOSFET threshold voltage (VTH) ranged from 4.4 V at 25°C to 2.2 V at 250°C and PMOSFET VTH ranged from -4.75 V at 25°C to just under -4 V at 300°C. The transfer threshold voltage (Vm) of the 4H-SiC CMOS inverter was in a very tight range of 2.8 V to 2.9 V over the entire temperature range of 25°C to 300°C when using a drive voltage (VDD) of 10 V.

Low dislocation density and even micropipe free substrates open up a great opportunity to produce high quality epitaxial layers. The epi-layer will become more sensitive to the epitaxial process itself and less dependent on varying substrate quality. Results presented here indicate a strong dependence of the epitaxial layers' growth mode and surface roughness on the substrates' dislocations and domain structure. Thick epitaxial layers grown on near on-axis wafers, both C-face and Si-face, show very similar growth behaviors as for physical vapor transport (PVT) grown crystals. The mix between step-flow and dislocation driven growth on near on-axis C-face chemical vapor deposition (CVD) grown epi-layers (30 μm thick) is resulting in a as smooth, and measured surface roughness is as low, as for growth on 8o off-axis substrates.

Surface roughness, Ra, measured on a 50 μm thick epitaxial layer, grown on a low EPD (1E+4 cm-2) 8o off-axis micropipe free substrate, was as low as 1.0 nm (2.98x2.32 mm area).

TiW(40 nm)/TiWN(80 nm)/Pt(500nm) was investigated as a new high-temperature compatible contact stack to 3C-SiC for harsh environment applications. Performance of TiW/TiWN/Pt contacts deposited on unintentionally doped (8.85×1018 cm-3) 3C-SiC grown by LPCVD to a thickness of ~1μm on (100) Si are reported. The linear transmission line method was used to determine specific contact resistance (ρc) at room temperature and for long-term tests at 300 °C. As deposited contacts were Ohmic with a ρc range of 1×10-4 to 1×10-3 cm2. These contacts were annealed for five minutes in forming gas (8% H2 92% Ar), at temperatures from 450 to 950 °C and all retained Ohmic character. Annealing samples at 450, 550 and 950 °C decreased ρc while anneling between 650 and 850 °C generally increased ρc.

Auger Electron Spectroscopy (AES) analysis was performed on a sample annealed at 750 °C. The as-received surface was composed of Si and O; after a brief sputter etch a characteristic Pt peak became visible and the O peak decreased substantially. Depth profiles detected Si throughout the Pt capping layer but not in the TiW layers. We suspect that Si diffuses from the SiC substrate into the Pt capping layer and surface Si also reacts with O2 to from an oxide. These reactions, in combination with incomplete SiC/TiW interface reactions, are suspected to cause the increase of ρc for samples annealed between 650 and 850 °C. Annealing at 950 °C gave the lowest contact resistance of 2.3×10-5. Long-term testing at 300 °C for 190 hours, in atmosphere, was performed on contacts annealed at 450 °C. When heated, the contacts initial ρc of 2.1×10-4 cm2 increased to ~4×10-3 cm2 which remained stable for the test duration. After long-term testing the sample ρc measured at room temperature decreased to 9.8×10-5 cm2.

A thermal anneal process has been developed that significantly enhances minority carrier lifetime (MCL) in bulk-grown substrates. Microwave photoconductivity decay (MPCD) measurements on bulk grown substrates subjected to this process have exhibited decay times in excess of 35 μs. Electron Beam Induced Current (EBIC) measurements indicated a minority carrier diffusion length (MCDL) of 65 μm resulting in a calculated MCL of 15 μs, well within the range of that measured by MPCD. Deep level transient spectroscopic (DLTS) analysis of samples subjected to this anneal process indicated that a significant reduction of deep level defects, particularly Z1/2, may account for the significantly enhanced lifetimes. The enhanced lifetime is coincident with a transformation of the original as-grown crystal into a strained or disordered lattice configuration as a result of the high temperature anneal process. PiN diodes were fabricated employing 350 μm thick bulk-grown substrates as the intrinsic drift region and thin p- and n-type epitaxial layers on either face of the substrate to act as the anode and cathode, respectively. Conductivity modulation was achieved in these diodes with a 10x effective carrier concentration increase over the background doping as extracted from the differential on-resistance. Significant stacking fault generation observed during forward operation served as additional evidence of conductivity modulation and underscores the importance of reducing dislocation densities in substrates in order to produce a viable bulk-grown drift layer.

Silicon carbide (SiC) substrates and epilayers contain many crystal defects, such as micropipes, screw dislocations, threading edge dislocations (TEDs), basal plane dislocations (BPDs) and stacking faults. To investigate these defects, synchrotron radiation topography is frequently carried out. When the monochromatic synchrotron X-ray topography is taken by the grazing-incidence reflection geometry using 11-28 reflection, screw dislocations, TEDs and BPDs are simultaneously seen and shown as different topographic images [1]. Many studies of dislocations were reported using 11-28 reflections in 4H-SiC [1,2]. Topographic images of the dislocations have been analyzed by the ray-tracing method of computer simulation [3]. However, experimental images of dislocations were not fully matched to the fine structure of simulation images, because of a lack of resolution in recording media: conventional films and nuclear emulsion plates [3]. This time, we report obtaining high-resolution topographic images using a new recording medium, and compare results between the experiment and the computer simulation. Synchrotron topography in 11-28 reflection was carried out at SPring8 applying holography films as high-resolution recording media. The TED images are distinguished as four types, which have ribbon-like features with different rotating angles, through the use of the films. The four different TED images agree well with the computer simulated images which have been reported by Vetter et.al. taking into account of the different Burgers vector directions [3]. By comparing the three topographic images taken at g=-12-18, 11-28 and 2-1-18, we confirmed experimentally that the four types of TED images originated from the difference of Burgers vector directions. We also investigated high-resolution topographic images of elementary screw dislocations, micropipes, and BPDs in 4H-SiC epilayers. The experimental image of screw dislocation fairly matched with simulated image. The fine features in the experimental topographic images of micropipes and BPDs are also compared with the simulated images in detail. [1] T. Ohno, H. Yamaguchi, S. Kuroda, K. Kojima, T. Suzuki, K. Arai: J. cryst. Growth. Vol. 260 (2004) 209. [2] H. Tsuchida, T. Miyanagi, I. Kamata, T. Nakamura, R. Ishii, K. Nakayama and Y.Sugawara: Jpn. J. Appl. Phys. Vol. 25, (2005), L806-808. [3] W. Vetter, H. Tsuchida, I. Kamata, M. Dudley: J. Appl. Cryst. Vol. 38, (2005), 442-447.

An 8° off-axis 4H-SiC wafer with circular Schottky contacts fabricated on a CVD grown 4H-SiC homoepitaxial layer was studied to investigate the influence of various defects, including small (closed-core) screw dislocations (Burgers vector of 1c or 2c), hollow-core (micropipes; Burgers vector larger than 2c), threading edge dislocations (from conversion of basal plane dislocations from the substrate into the epilayer), grain boundaries and triangular defects, on the device performance in the form of breakdown voltages. The defects were examined using synchrotron white beam x-ray topography (SWBXT) based techniques and molten KOH etching. The devices commonly contained basal plane dislocations, small screw dislocations and threading edge dislocations, the latter two of which could give rise to low breakdown voltages for the devices. In addition, less commonly observed defects such as micropipes, grain boundaries and triangular defects are much more destructive to device performance than closed-core screw dislocations and threading edge dislocations.

The effect of infrared absorption on SiC sublimation growth was numerically investigated. At first, absorption coefficient was estimated as function of doping concentration. Then temperature distribution inside a crucible was numerically analyzed with taking account of absorption in growing crystal. It was pointed out that temperature distribution in a growing crystal strongly depends on absorption coefficient, i.e. doping concentration. As increasing the absorption coefficient, the growth front temperature and temperature gradient inside a growing crystal increase. It might cause large thermal stress and affect the grown crystal quality. This agrees well with growth features in experiment. The growth condition should be determined with taking account of absorption coefficient, i.e. doping concentration.

Background doping as well as intentional doping using nitrogen and trimethylaluminum have been investigated for 4H-SiC epitaxy on offcut Si face, C face, and a-axis substrates over a wide range of C:Si ratio. Smooth morphology can be obtained at a C:Si ratio of 2.0 on a-axis substrates but not on Si or C face material. Background doping levels of <1 × 1015 cm-3 were achieved on a-axis and Si face material. Nitrogen incorporated much more efficiently on C face and a-axis as compared to Si face. Aluminum incorporated most efficiently on Si face and least efficiently on C face. Both of the above dopant incorporation trends were most pronounced at high C:Si ratios and were small or virtually absent at low C:Si ratios.

Carrot-like defects in a 7 off-cut (from [0001] toward <1-210> direction) 4H-SiC wafer with a 36μm thick 4H-SiC epilayer have been investigated using Nomarski optical microscopy, synchrotron white beam x-ray topography (SWBXT), scanning electron microscopy (SEM) and transmission electron microscopy (TEM). X-ray topographs confirm that threading screw dislocations are often associated with the carrots. Cross-sectional TEM observation confirms that a prismatic stacking fault exists below the carrot. This fault was found to show contrast in all observed diffraction geometries except for g=0004. A model for the mechanism of formation of this type of defect during epitaxial growth is proposed.

Vertical DMOSFET devices with sizes from single cell to 3x3 mm2 large devices have been fabricated on cubic 3C-SiC material. The used 3C-SiC substrates had varying material quality. The best quality had a more than 2 orders of magnitude lower density of extended crystal defects than the worst material. The processed and investigated vertical DMOSFET devices were designed for 600 V blocking voltage and had hexagonal unit cells with 2 μm channel length and aluminum implanted termination rings. The p-body was aluminum implanted and the source was phosphorus implanted. As deposited Ti/W contacts were evaluated as source and drain metallization. Single cell vertical DMOSFET devices, processed on the low defect density material quality, gave voltage blocking capabilities of more than 600 V with leakage currents of 0.1 to 10 μA. The same devices could handle currents around 5 mA in on-state at 15 V gate bias. MOSFET devices with 50 to 100 unit cells had blocking voltages of 400 to 500 V with on-state currents of 0.2 to 0.4 A at 15 V gate bias, indicating the potential of 3C-SiC for the fabrication of next generation power MOSFET devices.

Practical design of high-voltage SiC Schottky rectifiers requires the understanding of the influence of the epitaxial dopant concentration on the reverse and forward characteristics. This work analyzes the correlation between the dopant concentration and the I-V characteristics of Schottky diodes for a critical concentration range where the leakage current variations are more evident. The details of how high temperatures affect the properties of junctions have been carefully described to obtain further improvement in the future by proper device optimization. Dopant concentration of about 1.2 × 1016 cm-3 gives the best results in reverse characteristics without great losses in forward currents.

The growth rate of 4H-SiC epitaxial layer has been increased by a factor 19 (up to 112 μm/h) with respect to the standard process with the introduction of HCl in the deposition chamber. The epitaxial layers grown with the addition of HCl have been characterized by electrical, optical and structural characterization methods. The effects of different deposition parameters on the epitaxial growth process have been described in detail. This process can be very promising for high power devices with a breakdown voltage of 10 kV.

In this paper we present results of epitaxial layer deposition for production needs using our hot-wall CVD multi-wafer system. This equipment exhibits a capacity of 7x3” wafers per run and can be upgraded to a 6x4” setup. Characteristics of epilayers and reproducibility of the proc-esses are reported. Furthermore, we show recent results of p-type SiC homoepitaxial growth on 3” 4° off-oriented substrates using a single-wafer hot-wall CVD. The dependence of layer prop-erties on growth parameters, doping and thickness uniformity as well as doping memory effects are discussed. For the characterization of epitaxially grown pn-junctions first research grade pin-diodes were fabricated. The p-type emitters were either deposited in the same growth run to-gether with the n-type buffer and drift layers (continuous growth) or the n- and p-layers were grown in two different growth runs (separate growth).

Improved AlNi-based ohmic contacts to p-type 4H-SiC have been achieved using low energy ion (Al+) implantation, the addition of a thin Ti layer, and a novel two-step implant activation anneal process. Resistivities sometimes as low as 5×10−5 Ω-cm2 were reached by doping the surface region of lightly p-doped 4H-SiC epilayers via low energy Al+ implantation. Acceptor activation was achieved by annealing the samples with a 1400+1700°C two-step sequence in an Ar atmosphere, which also yielded improved surface morphology when implanted samples were capped with photo resist during the anneals. In this study, Ti/AlNi/W contacts on implanted layers were compared to Ti/AlNi/Au contacts. Even though the resistivities are higher than those of the Ti/AlNi/W system, the reduced anneal temperature, 650°C for Ti/AlNi/Au compared to 950°C for Ti/AlNi/W implies that Ti/AlNi/Au is a promising stacking configuration. Furthermore, the effects of a longer 30 minute anneal time at 600 − 700°C, in atmospheric pressure Ar ambients was observed. Namely, the 2 minute annealing cycle used for the Ti/AlNi/W study resulted in higher anneal temperatures before ohmic characteristics were seen. This same anneal time was not sufficient for the Ti/AlNi/Au samples, whereas increasing the cycle time to 30 minutes resulted in ohmic behavior at a much lower temperature. Increasing the anneal time however, had little or no impact on reducing the required anneal temperature of the Ti/AlNi/W.