The history of the semiconductor IC has often been dominated by the issues associated with transistor engineering. In recent years however, it has become clear that successful mastery of advanced logic devices depends not only on transistor engineering, but also on the ability to engineer and manufacture multiple level metallization systems to form the interconnect structure of modern and dense logic ICs.

In the next decade, it is expected that integrated circuits having 5 to 7 levels of metal will be common in VLSI technologies with linear interconnect densities approaching 200 meters/cm2/level. Multilevel interconnect technology needs are presently generating processing and structural issues which will dominate the future manufacturing yield and performance of these integrated circuits. The challenge of meeting these needs will require a concurrent improvement in design and manufacturing simplicity and cleanliness. This presentation will examine the architectural needs of future multilevel metal systems in light of the lithography, materials, and electrical requirements which must be addressed by the interconnect engineer. A comparison of interconnect systems based on different conductor materials will be presented.

Interconnect delay is shown to be a performance-limiting factor for ULSI circuits when feature size is scaled into the deep submicron region, due to a rapid increase in interconnect resistivity and capacitance. Dielectric materials with lower values of permittivity are needed to reduce the line-to-line capacitance as metal spacing decreases. However, the challenge is to successfully integrate these materials into on-chip interconnects. A new multilevel interconnect scheme has been developed that gives improved performance through insertion of a low-dielectric-constant material between metal leads. A novel polymer/Si02 composite dielectric structure provides lower line-to-line capacitance while alleviating many of the integration and reliability problems associated with polymers in standard interconnect processing.

The microelectronics industry is accelerating towards increasingly sophisticated circuit technology to interface with and drive a wide spectrum of products from low power to supercomputation systems. The base Si CMOS technology will span the applications such that optimization must be achieved by personalized wiring for each industry sector. As the feature size decreases to 0.25/µm or less, the interconnect metallization becomes a dominant technological challenge as circuit speeds, reliability and manufacturing costs are directly affected. The label "high performance" must now be defined in the context of the application. For example, as scaling proceeds for increased density and circuit speed, current density increase will impact lifetime by electromigration. Methods of simulation of fundamental degradation modes and design software tools must be developed and used in concert with performance simulation to optimize interconnect metallization ground rules early in the development cycle. Availability of such tools for interconnects is practically nonexistent, spurring significant focus on this direction by the materials community.

Copper metallization for on-chip multilevel interconnects is receiving increasing attention for future generations of ICs, with advantages of low line resistance, low interconnect delay, high electromigration resistance and, possibly, overall back-end process simplicity. However, copper introduces a set of processing and manufacturing issues which must be addressed in the research and development phases of the technology. This paper summarizes the most likely processing steps for integrating copper metallization into IC technology and presents the manufacturing issues (materials, unit processing and process integration issues) that need to be addressed.

Interconnections on silicon-based integrated circuits are almost exclusively aluminum alloys (Al-Si, Cu and various other solutes, e.g., Pd, Sc). The effects of film microstructure (grain size, grain size distribution, crystallographic texture and precipitate distribution) on the reliability of single level Al metallization has been well established. The final film microstructure obtained is dependent on both the deposition conditions and the thermal history during the manufacturing process. This paper will consider the role of microstructure in multi-level interconnects consisting of (1) AI(Cu) lines (in SiO2) with W and/or AI(Cu) studs and (2) an all Cu/polyimide multi-level structure. Methods for microstructure optimization during manufacturing of both Al and Cu based multilevel structures are explored. The variables important in determining the reliability of submicrometer single level versus multi-level structures and reliability testing methods (e.g., samples with versus without reservoirs and wafer level techniques) will be reviewed. Two relevant questions raised are; (1) What can be done during manufacturing to "build-in" reliability?, and (2) What are the trade-offs between manufacturing complexity (i.e., cost) and inherent reliability?

The optimization of electromigration (EM) and stress-induced voiding (SV) properties of advanced interconnects impacts many critical system design parameters. In particular, the choice of materials and manufacturing processes must be carefully planned during the early phases of product development. In layered metallizations, both the barrier and capping layers design can affect electromigration resistance and stress-relaxation behavior, while electrical performance often constitutes a trade-off. This is shown specifically in a study of titanium diffusion into Al-Cu from TiN barrier layers, and in initial stress-relaxation tests characterizing the effect of Ti addition in the capping layer. The development of advanced characterization techniques supports the trial-and-error experimental optimization process, but models predicting EM and SV reliability are needed and should include complex sets of microstructural and design parameters.

A submicron triple metal process for 0.5um logic CMOS is described, focusing on key process steps such as the dielectric planarization and metallization. The main emphasis has been placed on development of ar complicated planarization process utilizing SOG (Spin on Glass) etchback. In this paper, we report process data of triple metal technology which uses aluminum alloy for interconnects and P-TEOS (Plasma Tetra Ethyl Ortho Silicate) with siloxane SOG and etchback process for planarization.

Water entered into oxides when the oxides were indented with diamond in the presence of water or water vapor. Similar water entry is expected during silica glass polishing because of the high stress concentration on the glass surface in contact with small abrasive particles. Both chemical and mechanical properties of silica glasses change with water content. Polishing rate of silica in oil-based slurry with diamond abrasive increased with water content in the silica. Since oil has no chemical reactivity with silica, mechanical property degradation with water incorporation must be responsible for the fast polishing rate of the water-containing samples. A plausible mechanism of the polishing of silica is, therefore, water entry into silica under stress and mechanical removal of the altered layer. In the presence of water this process repeats itself.

Global Planarization requirements of the deep sub-micron technology generation requires use of CMP as preferred planarization technique. In the past, CMP has been used extensively in the polishing of silicon wafers. However , there has been some reluctance to utilize this technology in the planarization of oxide films during IC manufacture. This has been driven primarily by issues regarding manufacturability , and therefore cost of ownership of CMP processes. Here the key process integration issues in CMP planarization of oxide films are outlined.

An effect of consumable set is shown to be critical in achieving repeatable CMP performance via removal rate & non-uniformity. Various defects induced as a result of CMP are explained. Cost of ownership model is used to demonstrate the importance of minimizing such defects.

Chem-Mechanical Planarization (CMP) is a rapidly growing technology in the semiconductor fabrication repertoire. Initially offering an answer to the need for truly global planarization brought about by optical steppers' ever decreasing Depth of Focus (DOF), CMP may come to stay more for its impressive ability to actually decrease defect density, as well as potentially reduce the contact resistance of Tungsten plugs. But even the use of CMP at this post-etchback step first requires a manufacturable oxide planarization CMP technology, the single most difficult challenge of all the different CMP applications. In this presentation, We will describe various remaining mysteries of some of the more fundamental questions involving the process in addition to some present manufacturing issues.

Chemical mechanical polishing (CMP) is rapidly becoming the process of choice for planarizing dielectrics in very large scale integrated circuits. In addition, it is being used at an increasing rate in the removal of metals in order to define conducting levels. In the case of dielectric CMP, planarization ability is dictated by the mechanical aspects of polishing such as pad rigidity, polishing pressure and speed of the polishing platen, while inherent removal rate of the dielectric material is generally a function of the polishing chemistry. Polishing rate of both, dielectric and metallic films can be significantly increased by changing the nature of the dispersed abrasive in the slurry and that of the dispersing agent. However, such changes have profound implications to the surface quality, planarity, and cleaning of the polished surface. In addition, the polishing pad plays an important role in manufacturability of metal CMP processes. This work reviews the chemistry of polishing slurries containing silica, ceria and alumina abrasives for dielectric and metal CMP. Also, the contribution of the polishing pad to CMP processes is explained. The need for balancing the chemical and mechanical aspects of polishing in order to achieve overall planarization and pattern definition is demonstrated.

Three chemical processes that occur during the chemical mechanical polishing (CMP) of copper are described in terms of their effect on surface planarity, polish rate, and corrosion resistance of the polished copper. These processes are surface layer formation, dissolution of mechanically abraded copper, and chemical acceleration of the polish rate. The role of these processes is demonstrated with two slurry formulations used in the CMP of copper at Rensselaer.

This paper presents the results obtained from a systematic study on dielectric planarization using a chemical mechanical polishing (CMP) technique. This technique is readily applicable to intermetal and pre-metal dielectric films for advanced CMOS device fabrication. Results indicate that polishing rates vary with different dielectrics; with BPSG having the highest removal rate, while PECVD nitride having the lowest removal rate. Key parameters in determining the polishing rate are down force pressure and platen rotation speed. It is demonstrated that planarization becomes a reality on patterned wafers.

Halogen-based slurries have been investigated for chemical-mechanical polishing of tungsten. Among these slurries, Bromine-methanol-water slurry gives the best results. Depending on the polishing parameters and slurry concentration, polishing rate of the slurry for W varies from 100 nm/min to 300 nm/min, while the chemical etch rate of the slurry for W and SiO2 is near zero. The W and SiO2 films after polishing with the slurry show very smooth surfaces (featureless under a high quality optical microscope). The selectivity of larger than 15 has been achieved between W and PECVD TEOS oxide. Tungsten stud formation through CMP with this slurry has been demonstrated with no significant dishing in the metal.

Methods for determining planarization ability of CMP were explored. Options included film thickness measurements of the dielectric over metal and field, TIR measurements using profilometry, and a combination of the two. The attempt to observe the in situ change in the topography was addressed in two distinct experimental approaches. The first approach involved processing wafers for predetermined intervals. The other approach processed different wafers for different amounts of time. The effects of down force and platen rpm on planarization ability were studied using the first approach. Results indicate that planarization is more efficient at higher down forces and higher platen rpm. Slurry property effects were examined using the second method. The planarization ability appears to suffer at elevated pH values. This is attributed to both the enhanced solubility of the silica particles and the dielectric itself.

Chemical Mechanical polishing (CMP) is a useful technique for achieving global planarization in the ICs. The CMP of oxide has been used and studied for decades. Only recently the technique has been employed for planarizing the interlayer dielectric (ILD) on the silicon devices circuits. The effect of such polishing on the performance of the ILD has been the concern. This paper examines the attempts on defining the damage caused by CMP and its effect on the electrical properties after polished SiO2 wafers. In this investigation the PECVD and thermal oxide films were polished in the colloidal silica slurry on IC 60 pad. The polished oxide were then studied using I-V and nuclear reaction technique. The results show a surface damage which extends to about 800 Å in the polished oxide. The changes occurring in the concentration of hydrogenous species at the surface of SiO2 as determined by nuclear reaction technique will also be presented. It is shown that due to CMP as-deposited CVD SiO2 films loose water from surface regions whereas well annealed or dry oxides gain water at the surface. The results will be discussed and mechanisms will be presented to explain electrical results.

Before copper will be used in the manufacture of microelectronic circuits, a number of its surface and interface properties have to be addressed. These include corrosion resistance, adhesion to dielectrics, and ability to block the transport of copper ions from the metal into adjacent materials. Different schemes have been explored to meet copper's material properties needed for electronic application. For surface modification, these include ion implantation, plasma treatments, formation of surface silicides, and annealing of copper films doped with other elements. For interface control, most schemes have involved deposition of an adhesion/barrier film. The present paper will discuss our present understanding of the mechanisms that govern surface and interface passivation. Special attention will be given to schemes that might lead to both surface and interface passivation in the same process.

Recent findings concerning the surface chemistry of Cu(I)) and Cu(II) betadiketonate precursors on metal and TiN surfaces are reviewed. Interactions of Cu(I) hexafluoroacetylacetonate (L) (Cu(I)(hfac)(L); L=Lewis base) with the surface result in an adsorbed Cu(I)hfac intermediate. Cu(II)(hfac)2 adsorbtion yields the Cu(I)hfac intermediate plus adsorbed hfac. Subsequent exposure to atomic hydrogen volatilizes the adsorbed hfac and results in the reduction of Cu(I) via disproportionation: 2Cu(I)(hfac) ⇒ Cu(0) + Cu(II)(hfac)2 (desorbed). These results demonstrate that disproportionation can occur on contaminant free surfaces under UHV conditions, and that the mechanisms for Cu(I) and Cu(II)/H2 film growth are similar. Implications for selectivity and low temperature deposition are explored. Potential shortcomings of TiN as an adhesion/diffusion barrier are also discussed.

Thin copper films have been passivated by exposure to a dilute silane mixture (2% SiH4/Ar) at temperatures in the range of 225 - 375 °C. Previous XRD characterization indicates the surface layer to be Cu5Si[l]. Subsequently, the growth kinetics were examined by sheet resistance (Rs), RBS and step height measurements. Two distinct growth regimes are observed. The flow rate and time dependencies of the low temperature growth indicate parabolic solid state diffusion limited growth. The corresponding activation energy is 0.7 eV. A mass transport limitation is evidenced at higher temperatures. In addition, the biaxial stress and adhesion responses have been observed using the substrate curvature technique and scotch tape peel tests, respectively. A biaxial modulus (Eb) of 2.9x1011 Pa and coefficient of thermal expansion (CTE) of 8.6xl0-6 /°C have been determined from stress temperature cycling on Si and a-quartz substrates.