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Chemical Mechanical Polishing for Planarization in Manufacturing Environment

Published online by Cambridge University Press:  25 February 2011

Mukesh Desai ,
Rahul Jairath ,
Matt Stell  and
Robert Toiles
Mukesh Desai
Affiliation:
SEMATECH, 2706 Montepolis Drive,Austin,Texas-78741 On assignment from IBM Corp., Currently with SPEEDFAM Corp.
Rahul Jairath
Affiliation:
SEMATECH, 2706 Montepolis Drive,Austin,Texas-78741 On assignment from National Semiconductor Corp.
Matt Stell
Affiliation:
SEMATECH, 2706 Montepolis Drive,Austin,Texas-78741 On assignment from Digital Equipment Corp.
Robert Toiles
Affiliation:
SEMATECH, 2706 Montepolis Drive,Austin,Texas-78741 Currently with APPLIED MATERIALS Inc.
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Abstract

Global Planarization requirements of the deep sub-micron technology generation requires use of CMP as preferred planarization technique. In the past, CMP has been used extensively in the polishing of silicon wafers. However , there has been some reluctance to utilize this technology in the planarization of oxide films during IC manufacture. This has been driven primarily by issues regarding manufacturability , and therefore cost of ownership of CMP processes. Here the key process integration issues in CMP planarization of oxide films are outlined.

An effect of consumable set is shown to be critical in achieving repeatable CMP performance via removal rate & non-uniformity. Various defects induced as a result of CMP are explained. Cost of ownership model is used to demonstrate the importance of minimizing such defects.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 337: Symposium B – Advanced Metallization for Devices and Circuits—Science, Technology and Manufacturing III , 1994 , 99
Copyright
Copyright © Materials Research Society 1994

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References

REFERENCES

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