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A Multilayer Interconnect Process for 0.5um Logic Technology

Published online by Cambridge University Press:  25 February 2011

Donghyun Kim ,
H.S. Oh ,
K.Y. Lee ,
Y.S. Kim ,
B.S. Kim  and
B.G. Kim
Donghyun Kim
Affiliation:
Basic Technology Center, Samsung Electronics Co., Kihung, Republic of Korea.
H.S. Oh
Affiliation:
Basic Technology Center, Samsung Electronics Co., Kihung, Republic of Korea.
K.Y. Lee
Affiliation:
Basic Technology Center, Samsung Electronics Co., Kihung, Republic of Korea.
Y.S. Kim
Affiliation:
Basic Technology Center, Samsung Electronics Co., Kihung, Republic of Korea.
B.S. Kim
Affiliation:
Basic Technology Center, Samsung Electronics Co., Kihung, Republic of Korea.
B.G. Kim
Affiliation:
Basic Technology Center, Samsung Electronics Co., Kihung, Republic of Korea.
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Abstract

A submicron triple metal process for 0.5um logic CMOS is described, focusing on key process steps such as the dielectric planarization and metallization. The main emphasis has been placed on development of ar complicated planarization process utilizing SOG (Spin on Glass) etchback. In this paper, we report process data of triple metal technology which uses aluminum alloy for interconnects and P-TEOS (Plasma Tetra Ethyl Ortho Silicate) with siloxane SOG and etchback process for planarization.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 337: Symposium B – Advanced Metallization for Devices and Circuits—Science, Technology and Manufacturing III , 1994 , 81
Copyright
Copyright © Materials Research Society 1994

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References

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