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The Evolution of Chem-Mechanical Planarization: From Aberrant to Prosaic

Published online by Cambridge University Press:  25 February 2011

Peter Renteln
Affiliation:
National Semiconductor Corp., 2900 Semiconductor Dr., M/S E-100, Santa Clara, CA 95052
John Coniff
Affiliation:
National Semiconductor Corp., 2900 Semiconductor Dr., M/S E-100, Santa Clara, CA 95052
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Abstract

Chem-Mechanical Planarization (CMP) is a rapidly growing technology in the semiconductor fabrication repertoire. Initially offering an answer to the need for truly global planarization brought about by optical steppers' ever decreasing Depth of Focus (DOF), CMP may come to stay more for its impressive ability to actually decrease defect density, as well as potentially reduce the contact resistance of Tungsten plugs. But even the use of CMP at this post-etchback step first requires a manufacturable oxide planarization CMP technology, the single most difficult challenge of all the different CMP applications. In this presentation, We will describe various remaining mysteries of some of the more fundamental questions involving the process in addition to some present manufacturing issues.

Type
Research Article
Copyright
Copyright © Materials Research Society 1994

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References

REFERENCES

1 Renteln, P., Thomas, M. & Pierce, J., “Characterization of Chemical Mechanical Planarization Processes”, Proceedings of the 1990 VLSI Multilevel Interconnect Conference.Google Scholar
2 Warnock, J., “A Two-Dimensional Process Model for Chemimechanical Polish Planarization”, J. Electrochem. Soc. Vol 138, Nol.8 (1991)Google Scholar
3 Peter, Burke, “Semi-Empirical Modelling of Si02 Chemical-Mechanical Polishing Planarization”, Proceedings of the 1991 VLSI Multilevel Interconnect Conference.Google Scholar
4 Patrick, W.J., Guthrie, W.L., Standley, C.L., and Schiable, P.M., “Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit Interconnections”, J. Electrochem.Soc, Vol. 138, N. 6, June 1991 Google Scholar
5 Runnels, S., Journal of the Electrochemical Society, in PrintGoogle Scholar
6 Beyer, K.D., et al. , “Chem-Mech Polishing Method for Producing Coplanar Metal/Insulator Films on a Substrate”, U.S. Patent No. 4 944 836 (31 July 1990)Google Scholar
7 Pennington, S. and Luce, S., “Improved Process Latitude With Chemical-Mechanical Polishing, Proceedings of the 1992 VLSI Multilevel Interconnect Conference.Google Scholar
8 Kaanta, C.W., Bombardier, S.G., Cote, W.J., Hill, W.R., Kerszykowski, G., Landis, H.S., D.J, Poindexter, Pollard, C.W., Ross, G.H., Ryan, J.G., Wolff, S., Cronin, J.E., “Dual Damascene:A ULSI Wiring Technology”, Proceedings of the 1991 VLSI Multilevel Interconnect Conference.Google Scholar
9 Uttecht, R.R. and Geffken, R.M., “A Four-Level-Metal Fully Planarized Interconnect Technology for Dense High Performance Logic and SRAM Applications”, Proceedings of the 1991 VLSI Multilevel Interconnect Conference.Google Scholar
10 Jairath, R., Desai, M., Carpio, R., Stell, M., Toiles, R. and White, A., “Role of Consumables in the Chemical Mechanical Polishing (CMP) of Silicon Oxide Films”, Advanced Metalization for ULSI Applications Symp (1993)Google Scholar
11 Kishii, S., Horie, H., Hoko, M., Arimoto, Y., and Ito, T., “5000-um Line-and-Space Planarization Using Chemical Mechanical Polishing”, Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials, Makuhari (1993)Google Scholar
12 Shultz, L.D., Tuttle, M.E. and Doan, T.T., “Method for Planarizing Semiconductor Wafers with a Non-Circular Polishing Pad”, U.S.Patent # 5 234 867Google Scholar
13 Hu, A., Zhang, X., Sachs, E., and Renteln, P., “Application of Run by Run Controller to the Chemical-Mechanical Planarization Process”, IEEE/CHMT International Electronics Manufacturing Technology Symposium (1993)Google Scholar
14 Lai, W. Y-C., Miller, G.L., Schutz, RJ., Smolinsky, G., and Wagner, E.R., “Capacitive End-Point Detection for Oxide Planarization by Chemical-Mechanical Polishing”, Proceedings of the 1993 VLSI Multilevel Interconnect Conference.Google Scholar
15 Steigerwald, J.M., Murarka, S.P., and Gutman, R.J., “Electrochemical Effects on Chemical Mechanical Polishing and Corrosion Rate of Copper Films”, Techcon ‘93 suppression of Cu corrosion rate during polishingGoogle Scholar
16 Lakshminarayanan, S., Steigerwald, J., Price, D., Trogolo, J., Bourgeois, M., Chow, T.P., Murarka, S.P. and Gutmann, R.J., “Submicron Contact Structures with Copper Interconnects Fabricated by Dual Damascene Technology”, Techcon ‘93Google Scholar
17 Yu, C., Doan, T.T., and Grief, M., “A Novel Submicron Al Contact Filling Technology for ULSI Metallization”, Proceedings of the 1991 VLSI Multilevel Interconnect Conference.Google Scholar
18 Nguyen, C.T., Kuehne, S.C., Renteln, P., and Wong, S.S., “Quasi-SOI MOSFETs Using Selective Epitaxial Growth and Polishing”, IEDM Tech. Dig. (1992)Google Scholar
19 Webb, D., Sivaram, S., Stark, D., Bath, H., Draina, J., Leggett, R., and Tolles, R., “Complete Intermetal Planarization Using ECR Oxide and Chemical Mechanical Polish”, Proceedings of the 1992 VLSI Multilevel Interconnect Conference.Google Scholar
20 Ong, W., Robles, S., Sohn, S. and Nguyen, B.C., “Characterization of Inter-metal and Pre-metal Dielectric Oxides for Chemical Mechanical Polishing Process Integration”, Proceedings of the 1993 VLSI Multilevel Interconnect Conference.Google Scholar
21 Pierce, J.M., Renteln, P., Burger, W.R. and Ahn, S.T., “Oxide-Filled Trench Isolation Planarized Using Chemical/Mechanical Polishing”, ULSI Science & Tech Symp. of ECS (1991).Google Scholar
22 Poon, S., Sitaram, A.R., Fiordalice, B., Woo, M., Prinz, E., King, C., Gelatos, C., Perera, A., Burnett, D., and Hoffman, M., “Integration of Dielectric Chemical-Mechanical Polishing Technology in Advanced Circuits with Multilayer Interconnects”, Proceedings of the 1993 VLSI Multilevel Interconnect Conference.Google Scholar
23 Maury, A., Rodel Corp., Private Communication.Google Scholar