This study presents an investigation on physical-chemical stability of (HfO2)x(Al2O3 )1-x alloys upon prolonged post-deposition annealings. Two different Hf-aluminates were deposited by ALCVDTM, containing 34% and 74% Al2O3 mol% respectively. Post-deposition annealings (PDA) were carried out in O2 or N2 atmosphere, at 850°C and 900°C for 30 minutes. Interfacial layer (IL) increase after PDA was detected on all the samples, but with small differences between N2 and O2 treatments. Stack composition was characterized by means of XRR, XRF, RBS and TOF-SIMS. Growth of interface layer was justified by limited oxygen incorporation from external ambient. Silicon diffusion from the substrate into high-k material and aluminum/hafnium redistribution were observed and associated to annealing temperature. XRD and planar TEM analysis evidenced first grain formation and then, in the case of Hf-rich samples, almost complete crystallization. Overall, Hf-aluminates were found to remain XRD amorphous during high temperature prolonged treatments up to 900°C for 74% and 850°C for 34% alloys respectively. Differently from HfO2, (HfO2)0.66(Al2O3 )0.34 alloy was observed to crystallized in orthorhombic phase. Hf-aluminates were also electrically characterized by means of C(V) and I(V) measurements on basic capacitors. Variations in material electrical properties were found consistent with change in physical-chemical film structure. Increase in k value up to 30 was observed on Hf-rich samples crystallized in orthorhombic phase.

To improve short-channel characteristics and increase current drive, SOI technology is shifting focus from “classical” single-gate MOSFET architectures to multiple-gate device structures. This paper traces the history of single- and multiple-gate SOI MOSFETs and summarizes the electrical characteristics of such devices.

We show that SiGe grown on free-standing silicon is elastically relaxed. The free-standing Si structure consists of a ∼30 nm-thick, 5 μm-square silicon slab supported by a SiO2 pedestal at a single contact point at the center of the square (the cross-section resembles a mushroom). A matrix of free-standing structures was made by patterning a bonded silicon-on-insulator (SOI) wafer and undercutting the SiO2 to form the pedestal. Un-patterned areas of the SOI wafer and the exposed bulk Si substrate were included as reference regions. A UHVCVD Si0.8Ge0.2 film, about 200 nm-thick, was grown epitaxially on both sides of the free-standing silicon and the surrounding exposed bulk Si. The SiGe was also grown on the un-patterned SOI and bulk substrate control areas. The SiGe film grown on both SOI and bulk silicon was found to be fully strained. In contrast, the SiGe layer grown on free-standing silicon is ∼89% strain-relaxed, and the free-standing silicon film was measured to be under tensile strain. Since the same lattice mismatch was found between the SiGe layer and the Si on the free-standing silicon and on the SOI and bulk Si control regions, we conclude that the strain relaxation of the SiGe film on free-standing Si is elastic with the strain accommodated entirely by the free-standing silicon film under tensile strain. This was further confirmed by AFM measurements. The SiGe film on the control regions showed a very smooth SiGe surface with only a few surface steps originating from misfit dislocations at the SiGe/Si interface. No surface steps from misfit dislocations were observed on the surface of the SiGe film on free-standing Si. These results show that free-standing silicon serves as an ideal compliant substrate for SiGe.

A NiSi silicide process employing a Ni(Ti) alloy has been investigated. It was experimentally demonstrated that a small amount of Ti in Ni could overcome the reaction-inhibiting effect of an interfacial oxide layer on Si. Ti in the deposited Nil film reacts with the interfacial oxide, yielding an altered oxide layer, which acts as a Ni-permeable diffusion membrane during silicidation. Good diode characteristics were obtained from p+/n silicided Ni(Ti)-diodes with an initial interfacial oxide. It is believed that the ability to form silicide effectively in the presence of a native oxide will greatly relieve constraints on processing conditions and significantly enhance manufacturing yield.

Hafnium oxide (HfO2) thin films were synthesized from tetrakis(dimethylamino) hafnium (TDMAH) and ozone (O3) by atomic layer deposition (ALD) on 200 mm silicon wafers. Gradual saturation was observed for TDMAH exposure pulse. However O3 showed better saturation behavior for O3exposure. Yet, 100% step coverage was achieved for ~100nm trenches with aspect ratio of 35. Temperature dependence of the deposition rate was studied at susceptor temperature from 160°C to 420°C. The lowest deposition rate was observed at 320°C. Mercury probe measurements indicated the dielectric constant increased from 16 to 20 as susceptor temperature increased from 200°C to 320°C. Selected comparisons with tetrakis (ethylmethylamino) hafnium (TEMAH) were also made.

Because of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.

Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).

Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

For the fabrication of bulk strained Si devices, a thin Si layer is deposited on a virtual substrate consisting of a several μm thick compositionally graded SiGe layer. A simpler approach utilizing H or He implantation to enhance relaxation of a thin SiGe film was recently reported. In this current work, hydrogen implantation is used to enhance the SiGe relaxation; and, relaxation beyond the previous reported limit is demonstrated. Experiments are performed on CVD deposited SiGe films with Ge fractions ranging from 20% to 40 % and thickness in the range of 100nm to about 500nm. After annealing at 800°C, relaxation of more than 80% is achieved. PMOS and NMOS devices are successfully fabricated and much enhanced hole and electron mobilities are demonstrated.

Strained Si-based technology has imposed a new challenge for understanding dopant implantation and diffusion in SiGe that is often used as the buffer layer for a strained Si cap layer. In this work, we describe our latest modeling effort investigating the difference in dopant implantation and diffusion between Si and SiGe. A lattice expansion theory was developed to account for the volume change due to Ge in Si and its effect on defect formation enthalpy. The theory predicts that As diffusion in SiGe is enhanced by a factor of ∼10, P diffusion by a factor of ∼2, and B diffusion is retarded by a factor of ∼6, when compared to bulk Si. These predictions are consistent with experiment. Dopant profiles for As, P, and B were simulated using process simulators FLOOPS and DIOS. The simulated profiles are in good agreement with experiment.

Nitric oxide (NO) aided Si0.85Ge0.15 wet-oxynitridation has been performed at 400 700°C, while the wet-NO feed gas was preheated to higher temperatures before entering the reaction zone. X-Ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS) data suggests that both nitrogen and oxygen incorporation increases within the dielectric bulk with increasing wet-oxynitridation temperature, while there is no apparent germanium segregation towards the dielectric/substrate interface at all temperatures studied. Angle-resolved XPS analysis shows that increase in wetoxynitridation temperature above 600°C is likely to volatilize some germanium oxide from the surface region. Nitrogen incorporation is found to hinder germanium segregation. These results are discussed in the context of an overall mechanism of SiGe wet-oxynitridation.

We report the synthesis of new precursors Ba(thd)2(tmeea) and Sr(thd)2(tmeea), where tmeea = tris[2-(2-methoxyethoxy)ethyl]amine, and the LS-MOCVD of barium strontium titanate (BSTO) thin films using these precursors. Thin films of BSTO were grown on Pt(111)/SiO2/Si(100) substrates by LS-MOCVD using the cocktail source consisting of the conventional Ti precursor Ti(thd)2(OiPr)2 and the new Ba and Sr precursors. As-grown films were characterized by SEM, XRD, XRF, and C-V measurement. BSTO films grown at 420°C were stoichiometric barium strontium titanate with very smooth surface morphology and their dielectric constants were found to be as large as 320. The dependence of composition, microstructure and the electrical properties of the BSTO films on the growth temperature, annealing temperature, and working pressure will be discussed.

Schottky source/drain (S/D) in Si-CMOS provide an alternative to current approaches in S/D, channel, and gate-stack engineering. The Schottky S/D PMOS has been demonstrated at a number of university and industrial laboratories. The bottleneck for the Schottky S/D NMOS is the fact that none of the common metals or metal silicides has a low enough barrier height (~0.2 eV) on n-type Si. A method to produce low Schottky barriers on n-type Si with common metals including aluminum (Al) and chromium (Cr) is reported in this paper. The interface between metal and Si(100) is engineered at the atomic scale with a monolayer of selenium (Se) to reduce the density of interface states, and the engineered interface shows inertness to chemical and electronic processes at the interface. One consequence of this electronic inertness is that the Schottky barrier is now more dependent on the metal work function. Al and Cr both have work functions very close to the Si electron affinity. It is found that the Schottky barrier of Al on Se-engineered n-type Si(100) is 0.08 eV, and that of Cr is 0.26 eV. These numbers agree well with the ideal Schottky barrier heights for Al and Cr on n-type Si(100), but are significantly different from the barrier heights known for four decades for these metals on n-type Si(100). These results bring new hope for the Schottky S/D NMOS with a metal commonly used in the Si industry.

Boron segregation and its effect on carbon diffusion is studied in single-crystal Si1-yCy. We find that boron segregates from silicon to Si0.996C0.004 at a level m=[B]SiC/[B]Si = 1.7 during a 2 hour, 850°Cannealin N2. After this anneal, if most of the carbon is then removed from the Si1-yCy layer (via an oxidation-enhanced out-diffusion process), most of the boron segregation is removed as well. This argues against immobile B-C defects as the predominant mechanism driving the segregation. Boron is shown to increase carbon diffusion during the N2 anneal, but also appears to enhance carbon precipitation during a subsequent oxidation.

Due to integration concerns, the use of meta-stable junction formation approaches like laser thermal annealing (LTA), solid phase epitaxial regrowth (SPER), and flash annealing has largely been avoided for the 90nm CMOS node. Instead fast-ramp spike annealing has been optimised along with co-implantation to satisfy the device requirements, often with the help from thin offset spacers. However for the 65nm and 45nm CMOS node it is widely accepted that this conventional approach will not provide the required pMOS junctions, even with changes in the transistor architecture.

In this work, we will compare junction performance and integratablity of fast-ramp spike, flash, SPER and laser annealing down to 45nm CMOS. The junction depth, abruptness and resistance offered by each approach are balanced against device uniformity, deactivation and leakage. Results show that the main contenders for the 45nm CMOS are SPER and flash annealing – but both have to be rigorously optimised for regrowth rates, amorphous positioning and dopant and co-implant profiles. From the two, SPER offers the best junction abruptness (<1nm/dec) with leakage suitable for low power applications, while the flash anneal has the benefit of higher solid solubility (>4E20at/cm3) and less transistor modifications. As expected, Ge and F co-implanted spike annealed junctions do not reach the 45nm node requirements. For full-melt LTA, poly deformation on isolation can be reduced but geometry effects result in unacceptable junction non-uniformity.

Due to their compatibility with silicon interface and high dielectric constant, films containing hafnium oxide are becoming strong candidates in replacing silicon oxynitride as the gate dielectric layer in CMOS devices. To achieve ultimate conformality and thickness control, atomic layer deposition is receiving much more attention in recent years for nanometer size film applications. For hafnium oxide deposition by ALD, metal chlorides have traditionally been used as precursors with moisture being the co-reactant; however for gate oxide applications, metal chlorides are not considered suitable due to the corrosive nature of these compounds and the risks of film contamination. Hence, researchers are exploring alternate organometallic precursors in a CVD process with oxygen being the co-reactant. In this work, tetrakis (diethylamino) hafnium precursor is used in an ALD process with moisture co-reactant to deposit hafnium oxide films onto H-terminated Si substrate in a temperature regime of 200 to 350 C. Film composition is determined by x-ray analysis and is found to be stoichiometric without residue from ligand decomposition. Film thickness and uniformity is measured as a function of substrate temperature and reagent pulsing characteristics. These results will be presented and compared with that obtained with the more conventional hafnium chloride precursor.

Boron diffusion in germanium and relaxed Si1-xGex alloys with Ge content x>50% is reported. Relaxed SiGe layers were grown by LEPECVD and boron was introduced using ion implantation. Samples were given equal thermal budgets using furnace annealing. Diffusivity values of boron have been extracted. The results confirm that diffusion of boron in germanium is indeed slower than that reported in literature. The diffusivity of boron was found to increase gradually for x>50% at 900°C but the increase is not substantial. We found that pairing model is not sufficient to explain boron diffusivity behavior in SiGe alloys over the entire range of germanium content. The results suggest that an interstitial mediation of boron diffusion in germanium should be considered.

As the top Si layer is thinned, the dopants' diffusion in the confined Si layer in SOI wafer with respect to different thermal treatments needs to be better understood. Boron, BF2 with/without Ge pre-amorphization were implanted into bulk Si and SOI wafers with 530 Å Si and 1475A BOX. Samples were annealed using both spike (Impulse) anneal and Flash anneal. Simulations of dopant diffusion is used to resolve apparent differences in dopant profiles that resulted for SOI in contrast with bulk Si samples. Result suggests that the implantation damage difference between SOI and bulk Si makes the B diffusion in SOI higher than in bulk Si.

Relaxed, high Ge content SiGe layers have been realized using stress balance on a compliant borophosphorosilicate glass (BPSG). A 30-nm fully-strained Si0.7Ge0.3 layer was transferred onto a 1 μm BPSG film by wafer-bonding and Smart-cut® processes, after which the continuous Si0.7Ge0.3 film was patterned into small islands to allow for lateral expansion. After the strain in Si0.7Ge0.3 islands was released by the lateral expansion resulting from the flow of the BPSG, a Si0.4Ge0.6 layer was commensurately deposited under compression. Upon equilibrium after an annealing, stress balance was formed between the SiGe films, resulting in a larger in-plane lattice constant than that of relaxed Si0.7Ge0.3. With a thiner (6 nm) Si0.7Ge0.3 starting film, an in-plane lattice constant equivalent to fully-relaxed Si0.45Ge0.55 has been obtained.

In this work we investigate the diffusion and the electrical activation of In atoms implanted in silicon with different energies, in the range 80-360 keV, after rapid thermal processing. Our investigation shows a clear dependence of In out-diffusion and electrical activation on the implant depth, being the electrically active fraction higher with increasing the implant energy for a fixed dose. The data are explained considering the balance between the local In concentration and the C background inside the silicon substrate and the formation of C-In complexes, which play a role in the enhanced electrical activation due to the shallower level they introduce into the Si band gap (Ev+0.111 eV), with respect to the rather deep level (Ev+0.156 eV) of In alone. In and C co-implantation has also been studied within this work, in order to confirm the key role of C in the increase of the electrical activation. A large increase of the electrical activation has been detected in the co-implanted samples, up to a factor of about 8 after annealing at 900°C. However, C precipitation occurs at 1100°C, with dramatic effects on the carrier concentration.

Understanding charged defects in high dielectric constant insulators is a critical challenge for advanced devices. We have formed thin Zr and Hf silicates by oxidation of thin metal films sputtered on clean Si(100) and studied the effect of oxidation time (15 to 300s) and temperature (600 or 900°C) on the flatband voltage using capacitance vs. voltage measurements. We find that the thermal budget during oxidation and the type of oxidizing agent (slow vs. fast) affect the amount of fixed charge in the film significantly. Oxidation of 0.8nm of Zr metal on Si at 600°C in N2O for 15s results in EOT=1.2nm and a shift in the flatband voltage by ∼-0.2V indicating generation of positive fixed charge. Oxidation of similar films for 300s result in EOT=2.8nm and shift of the flatband voltage by ∼-0.95V. Hf films oxidized in N2O also show increased concentrations of fixed charge for longer oxidation times. By comparison, Si oxidized in the same environment does not show this extent of flatband voltage shift. A significantly reduced charge generation rate is observed for Hf oxidation under low O2 partial pressure. Extended oxidations (up to 1h) result in increased EOT and a slight decrease in the charged defect state density. Forming Gas Anneal (FGA) results in partial neutralization of the charge. FGA after the Al gate deposition also leads to significant decrease of the EOT (from 2.7 to 2.1nm) indicating significant reaction of the film with the gate metal. X-ray photoelectron spectroscopy for thin films indicates formation of Zr and Hf-silicates. However, for thick Hf films the low O2 oxidation process results in less silicon incorporation in the film as compared to films oxidized in N2O. Results suggest that understanding oxidation mechanisms will be important in isolating andcontrollingfixedchargeinhigh-kdielectrics.

In recent years there have been major advances in our understanding of the energetics, Ostwald ripening and transformations between various types of extended self-interstitial defect in Si and Ge ion-implanted silicon. As a result we can now predict the detailed time- and temperature-dependent supersaturation of interstitials during thermal evolution of these defects. This opens the way to predictive simulation of transient enhanced diffusion and dose loss in preamorphized ultrashallow junctions, where dopant movement is driven by free interstitials emitted by self-interstitial “end-of-range” defects. We present recent progress on this topic, emphasizing novel effects in highly doped ultrashallow junctions. Two key influences – the chemical pump effect due to the high concentration of dopants in ultrashallow junctions, and the ‘long hop’ behaviour of the dopant – are discussed in detail. The paper concludes by presenting simulation results that explain the recent observation of ‘uphill diffusion’ of B ultrashallow junction profiles.