A laser solid phase diffusion technique has been utilized to fabricate endolayers in n-type 6H-SiC substrates by carbon incorporation. X-ray energy dispersive spectrometry (XEDS) analysis showed that the thickness of endolayer is about 100 nm. High resolution transmission electron microscopy (HREM) images indicate that the laser endotaxy process maintains the crystalline integrity of the substrate without any amorphization. The resistivity of the endolayer was 1.1 ¡Á105 •cm and 9.4 ¡Á104 •cm after annealing at 1000C for 10 min. These resistivities provide device isolation for many applications. The silicon carbide endolayer was doped with aluminum using a laser doping technique to create p-region on the top surface of the endolayer in order to fabricate PIN diodes.

This paper updates recent progress made in growth, characterization, and understanding of high quality homoepitaxial and heteroepitaxial films grown on step-free 4H-SiC mesas. First, we report initial achievement of step-free 4H-SiC surfaces with carbon-face surface polarity. Next, we will describe further observations of how step-free 4H-SiC thin lateral cantilever evolution is significantly impacted by crystal faceting behavior that imposes non-uniform film thickness on cantilever undersides. Finally, recent investigations of in-plane lattice constant mismatch strain relief mechanisms observed for heteroepitaxial growth of 3C-SiC as well as 2H-AlN/GaN heterofilms on step-free 4H-SiC mesas will be reviewed. In both cases, the complete elimination of atomic heterointerface steps on the mesa structure enables uniquely well-ordered misfit dislocation arrays to form near the heterointerfaces with remarkable lack of dislocations threading vertically into the heteroepilayers. In the case of 3C-SiC heterofilms, it has been proposed that dislocation half-loops nucleate at mesa edges and glide laterally along the step-free 3C/4H interfaces. In contrast, 3C-SiC and 2H-AlN/GaN heterofilms grown on 4H-SiC mesas with steps exhibit highly disordered interface misfit dislocation structure coupled with 100X greater density of dislocations threading through the thickness of the heteroepilayers. These results indicate that the presence of steps at the heteroepitaxial interface (i.e., on the initial heteroepitaxial nucleation surface) plays a highly important role in the defect structure, quality, and relaxation mechanisms of single-crystal heteroepitaxial films.

Flash lamp annealing in the millisecond regime of heteroepitaxial silicon carbide on silicon structures involves melting the Si below the SiC layer, but the deep facetted nature of the solid-liquid interface leads to unacceptable surface roughness. This paper describes a method of controlling melting by implanting a high dose of carbon or germanium at a controlled depth below the Si/SiC interface, which significantly alters the melting characteristics of the silicon. Results confirm the effectiveness of these approaches for increasing surface uniformity, making liquid phase processing compatible with standard device fabrication techniques. A thermal model has also been developed to describe this process and results indicate that the theoretical work is consistent with the experimental evidence. The model is a valuable tool for predicting onset of melting, maximum temperatures and process windows for liquid phase epitaxy.

It is well-known that SiC crystal deficiencies are delaying the realization of outstandingly superior SiC power electronics. Efforts to date have centered on eradicating micropipes, and 4H-SiC substrates with extremely low micropipe densities have been achieved. Nevertheless, SiC substrates and epilayers still contain several types of dislocations in densities on the order of thousands per square centimetres, which are nearly 100-fold micropipe densities. While not nearly as detrimental to SiC device performance as micropipes, it has recently been demonstrated that dislocations existing in SiC crystals degrade several characteristics of SiC devices, e.g., the forward bias characteristics of SiC pin diodes and the gate oxide reliability of SiC MOSFETs.

This paper reports several dislocation processes occurring during the growth of hexagonal SiC bulk crystals. Particularly, we focus on the dislocation formation and propagation processes in SiC crystals. We have investigated dislocation processes in 4H-SiC bulk crystals grown by the physical vapor transport (PVT) growth method, using defect selective etching and transmission electron microscopy (TEM).

It was found that foreign polytype inclusions introduced a high density of dislocations at the polytype boundary. In the polytype-transformed areas of the crystal, very few medium size hexagonal etch pits due to threading screw dislocations were observed, indicating that the polytype transformation ceased the propagation of threading screw dislocations. The oval-shaped etch pit arrays observed on the etched vicinal (0001)Si surface, indicative of the dislocation multiplication in the basal plane, showed characteristic distribution around micropipes and low angle grain boundaries. Based on the results, we will argue the dislocation behavior in PVT grown SiC crystals, suggesting that dislocation interaction and conversion are relevant processes to understanding the behavior.

Schottky barrier diodes fabricated on Silicon carbide have been demonstrated as gas sensors for deployment in extreme environments. It has been shown that the interfacial layer formed at the Metal – Semiconductor junction, determines both the sensitivity and the reliability of the device. Hence, accurate knowledge of the thickness and interfacial trap density of this layer is required to make predictions of the behaviour of the sensor in the environment under investigation and to predict its variation with time. Diode parameters, such as the ideality factor, barrier height and series resistance have been extracted from experimental measurements on Palladium Schottky Barrier diodes on 4H SiC, over a range of temperatures. The comparison of the parameters extracted from modified Norde function, Cheung's method and Thermonic Emission model has been performed. The variation in the barrier height obtained is quite marked between the different techniques. The reverse I-V characteristics have been used to extract thickness of the interfacial layer, by fitting to the experimental data using the TEBIL model to extract the value of Dit from ä and the ideality factor, assuming the interfacial layer is stoichiometric SiO2 . This allows a comparison between the effective interfacial layer behaviour for the different parameter extraction techniques and demonstrates that knowledge of this interfacial layer is influenced by the technique selected.

Silicon carbide (SiC) materials, which are used in a variety of applications, are often produced using powder processing, sintering or bulk crystal growing techniques. The formation of silicon carbide films or shaped products, via these methods, is often extremely difficult and/or requires high temperatures. Here we report the synthesis and characterization of a polymeric precursor, Polymethylsilyne (PMSy), and it subsequent conversion to â-SiC. The polymer is simple to synthesize and is easily manipulated in air. The ceramic produced from PMSy is extremely pure, stoichiometric SiC and is produced in high yields (up to 85%). The ceramic films that can be produced from PMSy on a variety of substrates, from ceramics to metals, are again stoichiometric SiC and are smooth, continuous and defect free; possibly enabling the use of these films in electronic applications.

We have observed a gate-bias stress induced instability in both the threshold voltage of SiC MOSFETs and the flatband voltage of SiC MOS capacitors. The magnitude of this bias stress-induced instability generally increases linearly with log time, with no saturation of the effect observed, even out to 100,000 seconds. The magnitude also increases with increasing gate field. A positive gate-bias stress causes a positive shift and a negative gate-bias stress causes a negative shift, consistent with electron tunneling into or out of oxide traps near the SiC / SiO2 interface as opposed to mobile ions drifting across the gate oxide. The effect is repeatable.

This paper reports our effort to develop amorphous hydrogenated silicon carbide (a-SiC:H ) films specifically designed for MEMS applications using a semiconductor-grade organosilane known as trimethylsilane (3MS) as the precursor. In our work, the a-SiC:H films were deposited in a commercial PECVD system at a fixed temperature of 350˚C using 3MS diluted in helium (He). Films with thicknesses from ~ 100 nm to ~ 2μm, a typical range for MEMS applications, were deposited. Deposition parameters such RF power, deposition pressure, and 3MS-to-He ratio were explored to obtain films with low residual compressive stresses. Low temperature, post-deposition annealing at 450˚C was used to convert the as-deposited compressive residual stresses to moderate tensile stresses, which are desired for micromachined bridges, membranes and other anchored structures. Compositional analysis indicated that films with a Si-to-C ratio of 1 could be deposited under certain conditions. Mechanical properties such as Young's modulus and fracture strength were derived from the load-deflection behavior of micromachined freestanding membranes. Nanoindentation was used to verify the Young's modulus and determine the hardness. As expected, the films exhibit insulating properties with a relative dielectric constant at 3.90 for as-deposited films and 2.69 after annealing at 1100˚C, as determined from C-V measurements. Chemical inertness was tested in aqueous, corrosive solutions such as KOH and HNA. Prototype structures were fabricated using both surface micromachining and bulk micromachining techniques to demonstrate the potential of the a-SiC:H films for MEMS applications.

A study of temperature dependent Hall effect (TDH), electron paramagnetic resonance (EPR), photoluminescence (PL) and secondary ion mass spectrometry (SIMS) measurements has been made on high purity semi-insulating (HPSI) 4H-SiC crystals grown by the physical vapor transport technique. Thermal activation energies from TDH varied from a low of 0.55 eV to a high of 1.5 eV. All samples studied showed n-type conduction with the Fermi level in the upper half of the band gap. Carrier concentration measurements indicated the deep levels had to be present in concentrations in the low 1015 cm-3 range. Several defects were detected by EPR including the carbon vacancy and the carbon-silicon divacancy. PL measurements in the near IR showed the presence of the UD-1, UD-2 and UD-3 emission lines that have been found in HPSI material. No correlation between the relative intensities of the PL lines and the TDH activation energies was seen. SIMS measurements on nitrogen, boron and other common impurities indicate nitrogen and boron concentrations higher than those of individual deep levels as determined by TDH or of intrinsic defects as determined by EPR such as the carbon vacancy or the divacancy. It is determined that several different defects with concentrations greater than or equal to 1x1015 cm-3 are required to compensate the residual nitrogen and boron.

P-channel planar IGBT devices were made on 4H-SiC. Punch-through buffer and drift layers were designed to block 5 kV were grown on 4H-SiC n-type substrate. Ion implantion was used for all selective doping such as n-well, p+, n+, JFET region and terminations. Gate oxidation was thermally grown and annealed. Blocking voltage of 5.7 kV was demonstrated. IGBTs exhibit VTH of -12 V, VT = -3.1 V, Rdiff,on = 400 mΩcm2 at Vg = -34 V at room temperature. Ron decreased to 108 mΩcm2 at Vg = -30 V at 300°C.

The commercialization of 4H-SiC MOSFETs will greatly depend on the reliability of gate oxide. Long-term gate oxide reliability and device stability of 1200 V 4H-SiC MOSFETs are being studied, both under the on- and off-states. Device reliability is studied by stressing the device under three conditions: (a) Gate stress - a constant gate voltage of +15 V is applied to the gate at a temperature of 175°C. The forward I-V characteristics and threshold voltage are monitored for device stability, (b) Forward current stress – devices are stressed under a constant drain current of Id = 4 A and Vg = 20 V. The devices were allowed to self-heat to a temperature of Tsink = 125°C and the I-V curves are monitored with time, and (c) High temperature reverse bias testing at 1200 V and 175°C to study the reliability of the devices in the off-state. Our very first measurements on (a) and (b) show very little variation between the pre-stress and post-stress I-V characteristics and threshold voltage up to 1000 hrs of operation at 175°C indicating excellent stability of the MOSFETs in the on-state. In addition, high temperature reverse bias stress test looks very promising with the devices showing very little variation in the reverse leakage current with time.

The dependence of phosphorus doping on crystal face and C/Si ratio in the epitaxial growth of 4H-SiC using phosphine were investigated. Phosphorus incorporation was highest on off-axis (000-1) and lowest on off-axis (0001). Phosphorus incorporation on (11-20) came between that on off-axis (0001) and (000-1). With increasing C/Si ratio from 0.5 to 2.5, phosphorus incorporation increased on (11-20) and off-axis (000-1). Phosphorus incorporation on off-axis (0001) showed unclear C/Si ratio dependence. On (000-1), the highest phosphorus concentration of 2 × 1018cm-3 was obtained by an increasing PH3 flow rate. The roughness, growth rate, and surface morphology of the high phosphorus doped epilayer were investigated.

An optimized deep reactive ion etching (DRIE) process for the fabrication of SiC microstructures has been developed. The optimized process enables the etching of 4H and 6H SiC to depths > 100 microns with the required characteristics of (1) high rate (>0.5 microns/min), (2) vertical sidewalls, (3) minimal microtrenching at the sidewall base, and (4) smooth etched surfaces. The optimized process was determined based on the results of an experiment (full factorial design) which determined how the etch characteristics are affected by four important process parameters: temperature of the wafer chuck, pressure within the chamber, and concentrations of O2 and Ar in a gas flow comprised of O2, Ar and SF6. This study is believed to be the first systematic investigation of the effect of temperature on SiC DRIE characteristics; substrate heating was found to be a key in producing the desired etch properties.

Based on the various implanted standards, we have used SIMS (Secondary Ion Mass Spectrometry) to characterize SiC materials and devices. We develop the SIMS analysis on 2'' and 3'' full SiC wafers using our customized sample load chamber at a Cameca 4f magnetic sector SIMS tool. This feature is particularly useful for the on-line control of the wafer processing. With our special mounting skills, we provide SIMS analyses on small patterned area (say 50 microns × 50 microns or larger) of the tiny or large SiC dies. The detailed comparison between the implanted profiles for the major dopants (such as B, Al, and N) measured by SIMS and the simulated profiles by SRIM code [1] will be discussed. The detection limits for selected elements will also be discussed. In addition, it is well know that nitrogen has a very high ionization potential and zero electronic affinity. Therefore, nitrogen is normally profiled with a Cs+ primary beam and monitored negative molecular ions of (matrix+N)- [such as (Al+N)- in Al [2], (Si+N)- in Si, and (C+N)- in SiC]. However, such negative molecular detection mode cannot be applied to the multi-layers with different matrix elements (such as Al/SiC and Cu/SiC samples). Fortunately, like to detect nitrogen in Cu [3], we have found that using a Cs+ primary ion beam and monitoring (Cs2N)+ molecular ions by Cameca magnetic sector SIMS tools, nitrogen in the multi-layer samples including SiC layer can be detected by the (Cs2N)+ detection model [3,4] with a very low profiling energy (such as 2.5keV).

SiC homo-epitaxial layers were grown in a chemical vapor deposition process using silicon tetrachloride and propane precursors with hydrogen as a carrier gas. Growth rates were found to increase as temperatures increased at high carrier gas flow rate, while at lower carrier gas flow rate growth rates were observed to decrease as temperature increased. Based on the equilibrium model, “thermodynamically controlled growth” accounts for the growth rate reduction. The grown epitaxial layers were characterized using various techniques. Reduction in the threading screw dislocation (SD) density in the epilayers was observed. Suitable models were developed for explaining the reduction in the screw dislocation density as well as the conversion of basal plane dislocations (BPD) into threading edge dislocations (TED).

Films of MgO and MgCaO ternaries were grown at low temperature as dielectrics on 6H-SiC by gas-source MBE. MgO grown at 300 and 400°C revealed crystallites textured toward the (111) orientation on SiC (0001). A solid-solution Mg.75Ca.25O ternary was grown having a minimal lattice mismatch and low root mean square (RMS) roughness of 0.5 nm. SiC pretreatments in UV-ozone reduced carbon contaminants on the surface of SiC, but resulted in the increase of fixed oxide charge in the oxide/SiC interface. Electrical breakdown fields >3.5 MV cm-1 and low density of interface states on the order of 1011 cm-2eV-1 were achieved for a Mg.75Ca.25O ternary grown at 300°C. These oxides are presented for the first time as low temperature alternatives to SiO2 gate dielectrics for SiC MOS applications.

Structural, morphological and electrical characteristics of Al-implanted p+/n 4H-SiC diodes are compared for the same implantation process and post implantation annealing with identical stationary and cooling cycles but different heating velocity. Al+ ions were implanted at 400°C, with energies in the range 250-350 keV and total fluence of 1.2×1015 cm−2. Post implantation annealing processes were done at 1600°C for 30 min with a constant heating velocity in the range 7 – 40°C/sec and an abrupt cooling cycle. Gas in the annealing ambient was high purity Ar. The Al depth profile of annealed and as implanted samples were equal except for concentrations below 10E17 cm−3 where the former profiles showed a diffusion tail. With the increase of the heating velocity of the post implantation annealing process, sheet resistance of the Al implanted layer and diode leakage currents decrease while the surface roughness increases.

We describe surface preparation and epilayer growth techniques that readily reduce the density of Vf drift inducing basal plane dislocations in epilayers to less than 10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The optimal process route requires etching the substrate surface prior to epilayer growth to enhance the natural conversion of basal plane dislocations into threading edge dislocations during epilayer growth. The surface of this relatively rough “conversion” epilayer is subsequently repolished prior to growing the device structure. We provide details on processing parameters and potential problems as well as describe devices produced using this low basal plane dislocation growth processes.

Growth of thick SiC epilayers has been investigated in a horizontal hot-wall CVD reactor capable of growing 3x2-in wafers or single wafer with a diameter up to 100mm. Good uniformity of lower than 3% for thickness and lower than 20% for doping has been obtained on 2-in or 3-in epi wafers with thickness of 60 - 120 μm. Low intentional nitrogen doping of 5.8x1014 cm-3 was achieved on a 3-in epi wafer with a thickness of 120 μm. A higher growth rate of 10 μm/h was achieved while good uniformity was maintained. Surface morphology of the thick epilayers was carefully examined and smooth surface was observed for epilayers thicker than 100 μm. The defect density of the thick epilayers was also discussed and the high purity of the thick epi was verified by low temperature PL measurement.

Laser direct writing and doping has already been successfully demonstrated for fabrication of PIN diodes, Ohmic and Schottky contacts and other optical structures in silicon carbide (SiC). Although SiC is an indirect bandgap semiconductor a SiC green light emitting diode (LED) has been recently shown to perform better than a GaN green LED. This observation is primarily due to 1) a simple device structure in SiC as opposed to the multilayered structure in GaN and other high bandgap semiconductor compounds and 2) high thermal conductivity. This initial phase focuses on the fabrication of reference SiC LED's to baseline this novel laser direct writing and doping process.

6H:SiC (n-type) wafer samples were used for fabrication of LED's. A Nd:YAG laser (1064nm wavelength) was used in continuous wave mode as well as pulsed mode for doping. Doping process iterations were carried out to obtain a uniform doped layer. Two different techniques were employed for patterning: 1) top doping where the incident laser beam assists in doping on the top surface and 2) bottom doping where the bottom surface is doped using the same top incident laser beam. Different structures were synthesized using these two doping techniques. P-type dopants such as boron (in powder form) and aluminum (metalorganic compound tri-methyl aluminum) and n-type dopant (pure nitrogen gas) were used. The doped structures were characterized for I-V characteristics, C-V characteristics and electroluminescence.

Electroluminescence (EL) spectrum of the doped samples showed the output in the range of blue to blue green for different samples and the different doped structures. The feasibility of wavelength tuning using nanostructure patterning has also been explored.