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Do You Really Expect To Grow Epilayers On That? A Rationale For Growing Epilayers On Roughened Surfaces

Published online by Cambridge University Press:  01 February 2011

Joseph John Sumakeris
Affiliation:
[email protected], Cree, AD Epi, 4600 Silicon Dr., Durham, NC, 27703, United States, 9193135333, 9193135696
Brett A. Hull
Affiliation:
[email protected], Cree, Inc., 4600 Silicon Dr., Durham, NC, 27703, United States
Michael J. O'Loughlin
Affiliation:
Mike_O'[email protected], Cree, Inc., 4600 Silicon Dr., Durham, NC, 27703, United States
S. Ha
Affiliation:
[email protected], Carnegie Mellon University, Materials Science and Engineering, 5000 Forbes Ave., Pittsburgh, PA, 15213, United States
Marek Skowronski
Affiliation:
[email protected], Carnegie Mellon University, Materials Science and Engineering, 5000 Forbes Ave., Pittsburgh, PA, 15213, United States
John W. Palmour
Affiliation:
[email protected], Cree, Inc., 4600 Silicon Dr., Durham, NC, 27703, United States
Calvin H. Carter Jr.
Affiliation:
[email protected], Cree, Inc., 4600 Silicon Dr., Durham, NC, 27703, United States
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Abstract

We describe surface preparation and epilayer growth techniques that readily reduce the density of Vf drift inducing basal plane dislocations in epilayers to less than 10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The optimal process route requires etching the substrate surface prior to epilayer growth to enhance the natural conversion of basal plane dislocations into threading edge dislocations during epilayer growth. The surface of this relatively rough “conversion” epilayer is subsequently repolished prior to growing the device structure. We provide details on processing parameters and potential problems as well as describe devices produced using this low basal plane dislocation growth processes.

Type
Research Article
Copyright
Copyright © Materials Research Society 2006

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References

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