Based on a set of requirements identified for photonic crystals intended for use in optoelectronic devices, we have developed a method of fabricating three-dimensional photonic crystals that involves stacking air/semiconductor gratings by wafer fusion approach. Precise alignment of the stacked layers is achieved through the use of a laser beam assisted very precise alignment system, and three-dimensional photonic crystal has been successfully fabricated for the infrared and optical communication wavelength regions. We have also developed a photonic crystal waveguide providing sharp 90° bend.

Silicon pressure sensors have historically been fabricating by bonding a glass wafer to a micro-machined silicon wafer. The sensor may be sealed as an absolute pressure sensor by using planar glass and can then be used for detection of barometric pressure changes.

It has generally been assumed that as long as the glass and silicon are reasonable clean, then the silicon-glass seal is good and the part becomes a reliable, stable sensor. This paper addresses a low-level drift that was identified in such an absolute pressure sensor. A Zero drift in the range of 0.1% FS was detectable under humidity stresses. The stress always caused drift in the same direction, indicating an effective increased pressure in the sealed cavity.

The impact of various cleaning processes in reducing drift are reported. The improved process assure reliable product for applications such as automotive and altimeter applications.

We demonstrate a novel technique for fabricating monolithically series connected solar modules from surface structured thin monocrystalline Si films that we prepare by layer transfer using porous Si (PSI process). The novel series connection technique bases on reactive ion etching of the silicon film in a microwave plasma prior and after layer transfer. The module has an area of 25 cm2 and consists of 5 unit cells that have a film thickness of 16 µm. We measure an open-circuit voltage of 3028 mV and a confirmed efficiency of 9.9%. The Si film has a randomly textured surface for light trapping.

Direct wafer bonding can be used to mechanically and electrically connect semiconductors. In our experiments two 100 mm diameter (100) Si wafers (n-doping: 1014 cm−3) are first cleaned by standard chemical cleaning (RCA 1, 2). The surface is terminated by hydrogen after a HF dipping. The wafers are prebonded in air to protect the surface. After introduction into the ultra high vacuum (UHV) system the wafers are separated again. The hydrogen termination is released in a heating chamber. RHEED confirmed a surface reconstruction. The wafers are then cooled down to room temperature and bonded in UHV. The bonding energy is very close to the bulk bonding energy.

Measurements of whole n-n wafers showed a linear relationship of voltage and current at a low current density of 0.05 A/cm2. The current flow is inhomogeneous, which is visible in IR- thermography images. Above 0.1 V the current density first saturates, but increases super- linearly for higher voltages. The electrical properties of a grain boundary can be modeled by a double Schottky barrier. The barrier height decreases with increasing applied voltage. C-V measurements show a strong dependence of capacitance on frequency, temperature and applied voltage.

The capacitance increases with higher temperature and lower frequency. The interface state density can be estimated from the low temperature and high frequency capacitance limit as Dit = 1·1011 cm−2 eV−1 assuming a constant density of states.

We can conclude that in order to avoid the undesirable effect of the potential barrier and trap states at the bonding interface a high doping near the interface is required for the application of wafer bonding to devices with a high current density across the bonded interface.

A well-known process for thinning of silicon by slicing submicron-thick crystalline films from substrates uses direct implantation of protons. In this paper we describe a different way of delivering hydrogen to a cleavage plane. In our process a defect-rich buried layer is first formed with ion implantation. Defects in the as-implanted silicon work as traps for hydrogen. Next monatomic hydrogen is delivered to the trap layer by electrolytic charging. To check sliceability, the samples were annealed and blistering was observed. Evidence of blistering is a sign of potential cleavage. The electrolytic charging was performed using a simple two-electrode cell. The front side of the as-implanted silicon wafer was exposed to an electrolyte. The backside of the wafer was contacted with an aluminum layer and connected to a current source. The acidic electrolyte was buffered with ethylene glycol. Buffering was used to suppress bubbling on the wafer surface and to improve the uniformity of charging. To increase charging current the wafer was illuminated with visible light. A graphite rod was used as the positive electrode in the cell. A few Coulombs per square centimeter of the wafer were passed through the cell during the hydrogenation process. The depth of blisters is about 1/2 of projection range of the implanted ions. It means that the hydrogen platelets are formed in the region of maximum of vacancy- enriched post-implantation defects. This process of electrolytic hydrogen charging may be used in future to manufacture silicon-on-insulator wafers with very thin top silicon layer. Thin SOI offers important advantages in the production of substrates for mainstream CMOS integrated circuit manufacturing.

Direct waferbonding is an appropriate technology to join two or more wafers of the same or of different materials. Waferbonding can be used to stiffen thin wafers during fabrication. However, conventional fabrication processes lead to an increase of the bond strength, which inhibits the required de-bonding. The propagation of cracks, which is based on a subcritical crack growth in the bonded interface, was used to cleave the bonded wafers. The subcritical crack growth is limited to the bonded interface, since the adjacent bulk semiconductor materials are inherently resistant to subcritical crack growth. The process allows the separation of Si-Si and Si-GaAs wafers after annealing. Wafer-bonded SOI wafers can also be separated with this technology even if they were annealed at 1100°C. The first examples for wafer stiffening during fabrication and wafer transfer using the developed approach will be presented.

This paper reports on a novel, bonding-free method to fabricate silicon carbide-on-insulator (SiCOI) substrates. The process bypasses wafer bonding by using a high deposition rate polysilicon process in conjunction with wet chemical etching to produce wafer-thick polysilicon layers that serve as substrates for the SiCOI structures. Because wafer bonding is not used, insulators of various material types and thickness can be used. Using this method, transfer percentages over 99% are readily achievable. Various applications could benefit from this technology, including high temperature SiC-based microelectromechanical systems (MEMS) and SiC electronic devices.

Bonding of silicon surfaces in aqueous solution of compounds containing III and IV impurities was performed for the first time. It was observed that the presence of aluminum at the bonding interface improved structural quality of the interface. This phenomenon is explained by the increase of the contact area due to Al-OH group sandwiched between the water molecules adsorbed at hydrophilic wafer surfaces at the first bonding stage. The incorporation of Al produces a p-type layer and the I/V characteristics of the resultant np+n diodes is shown not to be influenced by the presence of the bonding interface. The technique developed could be advantageous for the design of multi-layer large area semiconductor devices.

A novel subminiature pressure sensor for blood pressure measurement has been fabricated. The device is only 250 microns wide and 70 microns thick. It is 1.1 mm in length. The sensor is housed in a guide-wire lead for use in measuring coronary artery blood pressure. The device has a 5 micron thick silicon diaphragm and senses pressure using a 1/2 bridge piezoresistive network. Glass is processed to provide depressions above the sensing area as well as above the connection area of the device. A full-thickness silicon wafer is processed using standard micromachining techniques. V-Groove notches are micro-machined on the top surface of the silicon to provide locators/guides for the lead-wires. Diaphragm windows are patterned on the back of the silicon wafer and the wafer is etched down to form the 5 micron diaphragm, using electro-chemical etch-stop techniques. The Glass and Silicon wafers are aggressively cleaned prior to bond. The glass and silicon wafers are then precisely aligned to better than 10 microns and bonded using anodic bonding techniques.

The glass/silicon wafer sandwich then has the silicon thinned from 400 microns to 37 microns using both grinding and polishing. Then the full-thickness glass wafer is etched in HF to a thickness of 37 microns as well, for a composite 74-micron thick structure. The wafer is then diced to form the micro-mechanical structure.

We have successfully used hydrophobic direct wafer bonding along with hydrogen-induced layer splitting of germanium to transfer 700 nm thick, single-crystal germanium (100) films to silicon (100) substrates without using a metallic bonding layer. The metal-free nature of the bond makes the bonded wafers suitable for subsequent epitaxial growth of layered solar cells at high temperatures without concern about metal contamination of the device active region. Contact mode atomic force microscopy images of the transferred germanium surface generated by the formation of micro-bubbles and micro-cracks along the hydrogen-induced layer-splitting interface reveals minimum rms surface roughness of between 10 nm and 23 nm. Electrical measurements indicated ohmic I-V characteristics for germanium layers bonded to silicon substrates with ∼400 Ω cm−2 resistance at the interface. Triple-junction solar cell structures grown on these Ge/Si heterostructure templates by metal-organic chemical vapor deposition show comparable photoluminescence intensity and minority carrier lifetime to a control structure grown on bulk Ge. The use of a molecular beam epitaxy Ge buffer layer to smooth the cleaved surface of the Ge heterostructure has been shown to smooth the rms surface roughness from ∼11 nm to as low as 1.5 nm with a mesa-like morphology that has a top surface roughness of under 1.0 nm giving a promising surface for improved solar cell growth on solar cell structures.

Plasma-treated and DI H2O rinsed oxide layers are commonly used in wafer bonding applications. Borosilicate glass (BSG) layers deposited by low-pressure chemical vapor deposition (LPCVD) treated with an O2 plasma in reactive ion etching (RIE) mode at 0.6 W/cm2 and rinsed with DI H2O readily bond to GaAs and Si. The chemical role of this pre-bonding treatment was investigated using attenuated total reflection Fourier transform infrared (ATR- FTIR) spectroscopy. The peak intensities for both the Si-O and B-O absorbance bands decreased in intensity as a result the plasma treatment consistent with the uniform sputter etching of BSG. The effect of changing the total plasma treatment time was investigated in terms of the total amount of material removed. Polarization-dependent ATR-FTIR revealed that the H2O/OH absorbance bands decreased in peak intensity with the OH groups preferentially oriented perpendicular to the sample surface after the plasma treatment. The subsequent DI H2O rinse restores the water to the surface while changing the surface BSG composition. ATR-FTIR studies suggest that for oxide compositions greater than 10 mole % B2O3, the top 4 nm of B2O3 was removed or leached from the oxide layer during the DI H2O rinse.

Molecular dynamics simulations using empirical potentials have been employed to describe atomic interactions at interfaces created by the macroscopic wafer bonding process. Investigating perfect or distorted surfaces of different semiconductor materials as well as of silica enables one to study the elementary processes and the resulting defects at the interfaces, and to characterize the ability of the potentials used. Twist rotation due to misalignment and bonding over steps influence strongly the bondability of larger areas. Empirical potentials developed by the bond order tight-binding approximation include ∏-bonds and yield enhanced interface structures, energies, and transferability to new materials systems.

Si/GaAs heterostructures were obtained by a low temperature direct wafer bonding (DWB) method which uses spin-on glass (SOG) intermediate layers. The use of intermediate SOG layers allows the fabrication of Si/GaAs heterostructures at processing temperatures lower than 200°C. The achieved bonding energy permits thinning down to a few microns of Si and GaAs wafers, respectively, using grinding procedures followed by chemical mechanical polishing (CMP). After thinning, the heterostructures sustained annealing temperatures of 450°C without damaging of the bonded interface. The above bonding procedure was successfully applied for bonding GaAs wafers to Si wafers with structured surfaces. A technology was developed based on this bonding method for producing universal GaAs-on-Si or Si-on-GaAs substrates.

SiC Lely platelets and SiC epilayers on large area SiC substrates were directly bonded to non-oxidized grooved surface silicon wafers in order to obtain structures prospective for the design of power bipolar devices with wide band-gap emitter junctions. The reported capabilities of grooved interfaces to reduce elastic strain and intrinsic sources of an interfacial potential barrier were utilized. The influence of surface morphology on the structural perfection of the bonded samples was studied in detail by X-ray and AFM techniques. As compared to traditional bonding technology, experimental data showed an easier smooth-to-grooved surface bonding accomplished in the formation of the boundary with better continuity and strength. For 2 in. diameter SiC wafers with root mean square height of roughness σ=16 Å and lateral coherence length L=1.8 μm bonding continuity not smaller than 90% was reached, while the crystals with σ=30 Å, L=5 μm failed to bond to Si even under an external force.

Most of the microelectromechanical systems (MEMS) require a 3-dimensional architecture which can efficiently be realized by multiple semiconductor wafer direct bonding. The present paper demonstrates the method on a force sensor for high resolution measurements of static loads. To minimize temperature stress an all-in silicon solution was developed in contrast to micromachined resonant force sensors published already in the literature.

The presented force sensor integrates load coupling, the excitation and detection of the vibration of the microresonator in one and the same single crystal silicon package. First measurements proved a sensitivity of 26 Hz/N and a resolution better than 3 mN.

Wafer bonding of SiC and GaN may prove important in the formation of high power heterojunction devices. Results of bonding SiC (C or Si surface) onto GaN (Ga surface) are presented. The samples were n-type 6H SiC and epitaxial n-type 2H(wurzite) GaN grown on SiC. The results demonstrate bonding for both possibilities, but the bonding of the C surface SiC to Ga surface GaN is more readily accomplished. A lower resistance was found for the C-face SiC/Ga-face GaN. The results indicate that the polarity of the interface is important for bonding of these materials.

ELTRAN is a unique technique to produce the SOI wafers using a porous Si material in semiconductor process. In ELTRAN process, it is required to form the porous Si layer on entire wafer surface uniformly, stably and mass productively without contaminations. In this investigation, we have carried out the simulation of current density distribution to unify the porous layer thickness by finite element method. Canon designed and completed an automatic anodization apparatus. As a result, we could produce the 8 and 6 inches porous Si wafers and ELTRAN SOI wafers stably. And we also developed successfully 300mm ELTRAN SOI wafers with excellent SOI film thickness uniformity.

Mechanical exfoliation strength has been measured in hydrogen implanted <100>, <111> and <110> oriented Si wafers using the crack opening method. The bonding temperature required for exfoliation increases in the order <100>, <111> and <110>. The same method has been applied to study the influence of boron doping on mechanical exfoliation in <100> Si wafers. The required bonding temperature to exfoliate mechanically decreases with increasing doping level independent of the electrical activation of boron. The enhanced crystallization rate of boron doped Si is suggested as a plausible explanation for the result.

InGaN-based optoelectronics have been integrated with dissimilar substrate materials using a novel thin-film laser lift-off process. By employing the LLO process with wafer-bonding techniques, InGaN-based light emitting diodes (LEDs) have been integrated with Si substrates, forming vertically structured LEDs. The LLO process has also been employed to integrate InGaN-based laser diodes (LDs) with Cu and diamond substrates. Separation of InGaN-based thin-film devices from their typical sapphire growth substrates is accomplished using a pulsed excimer laser in the ultraviolet regime incident through the transparent substrate. Characterization of the LEDs and LDs before and after the sapphire substrate removal revealed no measurable degradation in device performance.