To develop a high-κ gate dielectric for replacing SiO2 in MOSFETs, multi-component metal oxides could have advantages over single metal oxides because they may offer higher dielectric constants (κ's) as well as other favorable properties. To find the film composition for obtaining a good dielectric from the given component oxides is a time-consuming and costly process for multi-component systems. Recently, we reported a combinatorial chemical vapor deposition (CVD) technique to deposit compositional spreads of ternary metal-oxides for high-κ dielectrics. In this work, compositional spreads of ZrO2, TiO2, SnO2 and HfO2 were deposited using anhydrous metal nitrates. By measuring chemical composition, film thickness, and electrical properties, we are able to map κ and establish its dependence on film composition. This high-throughput deposition technique allows us to generate a compositional library quickly for screening material properties. In addition, a crystalline phase which does not exist in any of the four pure oxides, α-PbO2, was detected.

Carrier distributions associated with point charges in silicon solved with quantum perturbation theory are used to determine Coulombic interactions between charged defects in the presence of carrier screening. The resulting interactions are used in kinetic lattice Monte Carlo (KLMC) simulations of point defect-mediated diffusion to study dopant redistribution and associated variations in carrier concentration. Over a broad range of doping concentrations and temperatures, Coulombic repulsion between like dopants leads to ordering, resulting in a more uniform electrical potential distribution and therefore reduced variations in device performance compared with random doping, the standard condition assumed in previous doping fluctuation analyses.

The formation of an amorphous layer is needed to prevent channeling effect of B in the subsequent implant and hence, shallower as-implanted and annealed profiles could be expected. B diffusion in the pre-amorphization (PAI) Si has been studied extensively by many research groups and the diffusion has been explained by the interaction of B and defects generated by the PAI and B implant processes. In our previous study, we found that B diffusion can also be affected by the immobile B clustering caused by the incorporated species and therefore, B diffusion in the PAI Si should be expected to be different with different PAI species due to their different effect on the B clustering. In this paper, we reported different B diffusion behavior in bulk Si with respective to different PAI species. The species include GeF2, Ge, F, BF2, and In and the immobile B clustering plays an important role in the B diffusion reduction.

We studied the Pr2O3/Si(001) interface by a non-destructive depth profiling using synchrotron radiation and photo-electron spectroscopy (SR-PES) at the undulator beam line U49/2-PGM2 and ab initio calculations. Our results provide evidence that a chemical reactive interface exists consisting of a mixed Si-Pr oxide such as (Pr2O3)(SiO)x(SiO2)y. There is no formation of neither an interfacial SiO2 nor interfacial silicide: all Si-Pr bonds are oxidized and all SiO4 units dissolve in the Pr oxide. Under ultrahigh vacuum conditions, silicide formation is observed only when the film is heated above 800°C in vacuum. Interfacial silicates like (Pr2O3)(SiO)x(SiO2)y are promising high-k dielectric materials, e.g., because they represent incremental modification of SiO2 films by Pr ions, so that the interface characteristics can be similar to Si-SiO2 interface properties. The Pr silicate system formed in a natural way at the interface between Si(001) and Pr2O3 offers an increased flexibility towards integration of Pr2O3 into future CMOS technologies.

In this paper, we present our recent results on nickel germanosilicide contacts formed on p+-n and n+-p junctions formed by selective deposition of in-situ doped Si1-xGex alloys. Our results show that ultra-thin, low resistivity NiSi1-xGex contacts can be formed at temperatures as low as 300°C on both boron and phosphorus doped Si1-xGex layers. Ultra-shallow junctions with excellent reverse leakage behavior and a contact resistivity ∼ of 10-8 ohm-cm2 were successfully demonstrated. The thermal stability of NiSi1-xGex was found to be limited to 500°C on p+-Si1-xGex and 600°C onn+-Si1-xGex. It was found that by inserting a thin Pt interlayer between Ni and Si1-xGex, the quality of the NiSi1-xGex contacts could be significantly improved. The Pt interlayer was found to improve the interface morphology, which was found to have a direct impact on the electrical properties of the contacts.

In the present experiment, we have grown 2500-Å thick Si0.75Ge0.25 alloy layers on Si(001) substrate by MBE process using a short-period (Si14/Si0.75Ge0.25)20 superlattice (SL) as buffer layers. In the SL layers, first a layer of 14 monolayers (MLs) of Si (thickness about 20Å) then a thin layer of Si0.75Ge0.25 (thickness 5-6Å) were grown. This Si/(Si0.75Ge0.25) bilayers were repeated for 20 times. The buffer layers were grown at different temperatures from 300-400°C and the alloy layers were then grown at 500°C on the buffer layers. The alloy layer showed low residual strain (about -0.16%) and smooth surface (rms roughness ~15Å) with 300°C grown SL buffer. Low temperature growth of Si in SL layer introduces point defects and low temperature growth of Si1-xGex in SL layer reduces the Ge segregation length, which leads to strained SL layer formation. Strained layers are capable to make barrier for the propagation of threading dislocations and point defect sites can trap the dislocations.

Formation of ultra-shallow junctions by excimer laser annealing (ELA) of ultra-low energy (1keV –250 eV) B implanted in Si has been investigated. High resolution TEM has been used to assess the as-implanted damage and the crystal recovery following ELA. The electrical activation and redistribution of B in Si during ELA has been studied as a function of the laser energy density (melt depth), the implant dose and the number of laser pulses (melt duration). Under appropriate ELA conditions, ultra-shallow profiles, extending to a depth as low as 35 nm with an abrupt profile (2.5 nm/dec), have been achieved. A significant amount of the implanted dopant was lost from the sample following ELA. However, the dopant that was retained in crystal material was fully activated following rapid re-solidification. We developed a theoretical model, that considers the dopant redistribution during melting and regrowth, showing that the fraction of the implanted dopant not activated during ELA was lost from the sample through out diffusion. The lateral distribution of the implanted B following laser annealing has been studied with 2-D measurements, using selective etching and cross-section TEM on samples where the implanted dopant was confined by using test structures including windows opened in silicon dioxide masks and patterned gate stack structures.

The use of alternative channel materials such as germanium [1,2] and strained silicon (ε-Si) [3-5] is increasingly being considered as a method for improving the performance of MOSFETs. While ε-Si grown on relaxed Si1-x Gex is drawing closer to widespread commercialization, it is currently believed that almost all of the performance benefit in CMOS implementations will derive from the enhanced mobility of the n -MOSFET [5]. In this paper, we demonstrate that ε-Si p -MOSFETs can be engineered to exhibit mobility enhancements that increase or remain constant as a function of inversion density. We have also designed and fabricated ε-Si / ε-Ge dual-channel p -MOSFETs exhibiting mobility enhancements of 10 times. These p -MOSFETs can be integrated on the same wafers as ε-Si n -MOSFETs, making symmetric-mobility CMOS possible.

We investigate diffusion and segregation of Sb and As after low energy implantation and annealing. Sb implantation profiles are significantly more stable against segregation for implantation energies higher than 5 keV compared to As. For ultra-shallow profiles and annealing temperatures above 850°C we demonstrate strong Sb and As segregation up to 1021 cm–3 in an interfacial layer less than 3 nm. In comparison to As antimony profiles show reduced tails mainly due to less sensitivity for excess Si self-interstitial effects generated both during implantation defect anneal and during deactivation of heavily n-doped regions by clustering.

To facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

One of the grand challenge imposed by CMOS down-scaling is the optimisation of the source/drain (S/D) architecture, e.g., dopant activation above solid solubility, steep dopant profiling, low silicide specific contact resistivity. Recently, the concept of very low Schottky barrier S/D MOSFET has emerged as a possible alternative to conventional architecture using highly doped S/D and midgap silicide ohmic contacts. For p-MOSFETs integration, platinum silicide is an excellent candidate because of its very low barrier to holes. This enables the use of a weakly doped substrate that inherently solves the aforementioned challenges due to highly doped S/D. This paper proposes a detailed study of the platinum silicidation reaction obtained by rapid thermal annealing. The analysis is based on X-ray photoemission spectroscopy (XPS), transmission electron miscrocopy (TEM) and low temperature-dependent current-voltage measurements. Using XPS analysis, it is shown that: i) an initial silicide layer is formed at room temperature, ii) three stable phases Pt, Pt2Si, PtSi can not coexist providing that iii) the annealing ambience is strictly controlled to avoid the formation of a SiO2 barrier due to oxygen penetration into the platinum overlayer. Starting from an initial 15 nm thick Pt layer subsequently annealing at 300°C, TEM cross-sections reveal that homogeneous 32 nm PtSi layers with a uniform grain size distribution are formed. Finally, current-voltage characteristics have been measured on a special test structure that accounts for the lateral disposition of S/D regions in a typical MOSFET architecture. It consists in two back-to-back Schottky contacts separated by a narrow silicon gap both on bulk silicon and Silicon-On-Insulator (SOI) substrates. Based on temperature-dependent electrical measurements (Arrhenius plot), it is shown that field emission is involved in the current transport mechanism, in addition to thermionic emission. An excellent current drive performance of 220 μA per micron width has been obtained for a 45 nm silicon gap on a 10 nm thick SOI substrate.

High-κ dielectrics based the oxide of Al were prepared by atomic layer deposition (ALD) on 200-mm p-type Si wafers. Films were deposited directly on clean Si or on 0.5-nm underlayers of rapid thermal oxide or oxynitrides grown in O2 and/or NO ambients. The purpose of the underlayer films is to provide a barrier for atomic diffusion from the crystal Si to the high-κ dielectric film. Deposited Al-oxide films varied in thickness from 2 to 6 nm. Post deposition anneals were used to stabilize the ALD oxides. Equivalent SiO2-oxide thickness varied from 1.0 to 3.5 nm. In situ P-doped amorphous-Si 160 nm films were deposited over the oxides to prepare heavily doped n-type gate electrodes in MOS structures. Samples were rapid thermal annealed in N2 ambient at 800°C for 30 s, or spike annealed at 950, 1000, and 1050°C (nominally zero time at peak temperature). Flat band voltages, VFB were determined from C-V measurements on dot patterns. The 800°C anneals were used as a baseline, at which the poly-Si electrodes are crystallized and acquire electrical activation while subjecting the high-κ dielectrics to a low thermal budget. Positive shifts in VFB were observed, relative to a pure SiO2 control, ranging from 0.2 to 0.8 V. Spike annealing reduces the VFB shift for ALD films deposited over underlayer films. The VFB shift and the changes with annealing temperature show systematic dependence on the nitridation of the underlayer.

A process involving implantation mediated selective etching has been developed for Source/Drain elevation of CMOS devices. 100 nm thick epitaxial silicon/polysilicon layer was formed on patterned Si/SiO2 structure by chemical vapor deposition (CVD) at 700°C. Structural damage was selectively introduced in polysilicon layer by a low dose Argon implantation at 140 keV. Crystal damage in epitaxial silicon layer was kept minimum by aligning the implantation in vertical <100> channeling direction. A short duration post-anneal at 420°C was usedfor structural recovery of the silicon layer. Polysilicon layer was then removed by wet etching with more than an order of magnitude selectivity over epitaxial silicon. The resulting structure of elevated silicon is free from faceting effects. The process is independent of sidewall/isolation materials, and not bound by thickness limits.

We propose a new parameter predicating transconductance (Gm) of the gate dielectric of nitrided SiO2 with the physical thickness below 1.1 nm for high-performance transistors. The 6 different type of nitrided SiO2 are formed using the plasma nitridation or nitric oxide (NO) gas annealing in conditions to adjust a optical thickness ranging 0.96 to 1.19 nm. The material property of nitrided SiO2 are analyzed by secondary ions mass spectroscopy (SIMS) and x-ray photoelectron spectroscopy (XPS). The MOSFET are fabricated using these gate dielectric and 90 nm generation CMOS technology. Then we find a good correlation between the maximum of Gm and the percentage of amount of N(SiN3)3 substructure at the total amount of NSi3 structure measured by XPS, rather than the total dose of nitrogen measured by SIMS.

In the quest for ever smaller transistor dimensions, the well-known and reliable SiO2 gate dielectric material needs to be replaced by alternatives whith higher dielectric constants in order to reduce the gate leakage. Candidate materials are metal oxides such as HfO2. Themost promising deposition techniques, next to Physical Vapor Deposition, appear to be ALCVD and MOCVD. In this paper, we compare the most important characteristics of layers from both proces techniques and assess their relevance to gate stack applications: density, crystallisation, impurities, growth mechanism, interfacial layers, dielectric constant, mobility. Although we find some minor differences, layers from both techniques mostly show striking similarities in many aspects, both positive and negative.

Various mechanical and chemical processes may introduce contamination, such as metallic ions, during the creation of an integrated circuit. This can cause device degradation and leakage current. Neutral dopants such as boron can penetrate the silicon substrate from a highly doped polysilicon gate during anneal cycles causing leakage and threshold voltage shifts. Quantum mechanical modeling using periodic boundary conditions and a cluster approximation were performed in a search for a modification of silicon dioxide that would attract or trap ions and fast diffusing dopant species to reduce or eliminate such problems. Examination of calcium and strontium interactions with some metal ions in silicon dioxide was conducted. Strong metal ion attraction to both calcium and strontium was found. Interaction of calcium with boron and fluorine in oxide and calcium interaction with boron in other dielectric materials was also studied. Attraction was predicted to occur between calcium and boron whether they were distributed in silicon dioxide, hafnium or zirconium orthosilicate. This study leads us to propose incorporation of calcium or strontium into critical dielectric layers as a promising approach to trap ions and reduce boron penetration through the gate oxide. Predictions were used to design relevant experiments which revealed that calcium implanted into oxide traps boron and fluorine.

Two layer metal gate stacks allow the effective work function to be tuned by varying the thickness of the first metal layer. Metal-oxide-semiconductor (MOS) capacitors were fabricated by using two metals of very different work functions on thermal oxide gate dielectric where the bottom layer thickness is varied over a range from 0 to 50nm. Electrical and thermal stability measurements were performed on the Al on TaN metal gate stack. The effective workfunction is seen to shift from the value of one metal to the other rapidly as the thickness of the first metal layer is varied from 0 to approximately 10nm. The flat band voltage (Vfb) transition matches the workfunction difference of the two metals in the stack. The advantage of this approach when applied to metal-oxide-semiconductor-field-effect-transistors (MOSFETs) is that it allows the effective workfunction of the metal stack, and the threshold voltage (Vth) of the device to be fine tuned. It also allows for eventual dual gate complementary MOS (CMOS) device fabrication where two different work function metal stacks are necessary, without processing directly on the gate dielectric. A model is proposed to elucidate the workfunction tuning mechanism.

One of the major advantages of multiple-pulses Laser Thermal Annealing (LTA) with moderate energy fluence is that good dopant activation can be achieved without further increases in junction depth by successive pulses. It is demonstrated that when the laser fluence is adjusted to a value that can melt the preamorphization implantation (PAI) layer but not the underlying silicon substrate, PAI layer depths control the junction depths. Hence, it is desirable to operate LTA in this regime since this allows for a tighter process control as opposed to when the junction depth is controlled solely by the laser fluence. High Resolution Transmission Electron Microscopy (HR-TEM) micrographs show that the degree of damage repair depends on the amorphous layer thickness as well as the number of pulses. Our study allows for the evaluation of the maximum allowable PAI depth for a given number of pulses in order to fully remove the damage caused by the PAI.

A cleaning process resulting in atomically smooth, hydrogen-terminated, silicon surface that would inhibit formation of native silicon oxide is needed for high-k gate dielectric deposition. Various cleaning methods thus need to be tested in terms of resistance to native oxide formation. Native oxide re-growth is studied as a function of exposure time to atmospheric ambient using ellipsometry. Hafnium dioxide film (k ~23) is deposited on the as-cleaned substrates by electron beam evaporation and subsequently annealed in hydrogen. The difference in the effective oxide thickness re-grown on surfaces treated with the conventional RCA and modified Shiraki cleaning methods, after one-hour exposure, can be as large as 2 Å. This is significant in device applications demanding equivalent oxide thickness less than 20 Å. The degree of hydrogen passivation, surface micro-roughness and organic removal capability are considered to be the main factors that explain the differences between the cleaning methods. Data derived from capacitance-voltage analysis of test capacitors verified the trend observed in the native oxide thickness measurements. An increase of 10~15 % in accumulation capacitance is observed in the samples treated by the new cleaning method.

NiSi-silicided p+n shallow junctions are fabricated using BF2+ implantation into/through thin NiSi silicide layer (ITS technology) followed by low temperature furnace annealing (from 550 to 800°C). The NiSi film agglomerates following a thermal annealing at 600°C, and may result in the formation of discontinuous islands at a higher temperature. The incorporation of fluorine atoms in the NiSi film can retard the formation of film agglomeration and thus improve the film's thermal stability. A forward ideality factor of about 1.02 and a reverse current density of about 1nA/cm2 can be attained for the NiSi(310Å)/p+n junctions fabricated by BF2+ implantation at 35 keV to a dose of 5×1015cm-2 followed by a 650°C thermal annealing; the junction formed is about 60nm measured from the NiSi/Si interface. Activation energy measurements show that the reverse bias junction currents are dominated by the diffusion current, indicating that most of the implanted damages can be recovered after annealing at a temperature as low as 650°C.