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Impact of Gate Process Technology on EOT of HfO2 Gate Dielectric

Published online by Cambridge University Press:  01 February 2011

Daewon Ha ,
Qiang Lu ,
Hideki Takeuchi ,
Tsu-Jae King ,
Katsunori Onishi ,
Young-Hee Kim  and
Jack C. Lee
Daewon Ha
Affiliation:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
Qiang Lu
Affiliation:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
Hideki Takeuchi
Affiliation:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
Tsu-Jae King
Affiliation:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
Katsunori Onishi
Affiliation:
Department of Electrical and Computer Engineering, University of Texas, Austin, TX, USA
Young-Hee Kim
Affiliation:
Department of Electrical and Computer Engineering, University of Texas, Austin, TX, USA
Jack C. Lee
Affiliation:
Department of Electrical and Computer Engineering, University of Texas, Austin, TX, USA
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Abstract

To facilitate CMOS scaling beyond the 65 nm technology node, high-permittivity gate dielectrics such as HfO2 will be needed in order to achieve sub-1.3nm equivalent oxide thickness (EOT) with suitably low gate leakage, particularly for low-power applications. Polycrystalline silicon-germanium (poly-SiGe) is a promising gate material because it is compatible with a conventional CMOS process flow, and because it can yield significantly lower electrical gate-oxide thickness as compared with poly-Si. In this paper, the effects of the gate material (Si vs. SiGe) and gate deposition rate on EOT and gate leakage current density are investigated. Poly-Si0.75Ge0.25 gate material yields the lowest EOT and is stable up to 950°C for 30 seconds, providing 2 orders of magnitude lower leakage current compared to poly-Si gate material. A faster gate deposition rate (achieved by using S2H6 instead of SiH4 as the gaseous Si source) is also effective for minimizing the increases in EOT and leakage current with high-temperature annealing.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 765: Symposium D – CMOS Front-End Materials and Process Technology , 2003 , D2.2
Copyright
Copyright © Materials Research Society 2003

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