3D integration enabled by through-silicon-via (TSV) allows continued performance enhancement and power reduction for semiconductor devices, even without further scaling. For TSV wafers with all Applied Materials unit processes, we evaluate the integrity of oxide liner and copper barrier by capacitance-voltage (C-V) and current-voltage (I-V) measurements, from which oxide capacitance, minimum TSV capacitance, and leakage current are extracted. The capacitance values match well with model predictions. The leakage data also demonstrate good wafer-scale uniformity. The liner and barrier quality are further verified with microanalysis techniques.

Metal Nickel(Ni) fill becomes the challeng in integrating silicide-last process into CMOS advanced technology with further contact size scaling. In this work, the specific contact resistivity (ρc) of cold titanium(Ti)/Si was investigated by the cross-bridge Kelvin resistor(CBKR) method and compared with that of Ni(Pt)Si/Si. The cold Ti/n+-Si showed comparable contact resistance(ρc∼3x10-8Ω·cm2) to Ni(Pt)Si/ n+-Si, while a larger ρc(7.5x10-1Ω·cm2) for cold Ti formed on B+ doped Si substrates. The cold Ti/Si interface was also discussed. Our results furnish a fresh perspective on the solutions to the metal fill challeng for silicide-last process.

We describe a mass transport TCAD simulation by using a Sentaurus S-Interconnect tool [1] that models reported electro-migration (EM) behaviors: EM induced resistance (R) change, line length (L) effect, and temperature (T) dependency on L and current density (j) products. We performed trend and sensitivity analyses for key physical EM model parameters: Cu-void formation, a sudden jump in line R associated with void growth, and Cu-vacancy (Cv) and void (Cvoid) profiles. In this manner, we develop a new methodology for accurately determining the EM lifetime by identifying an “EM-aware” region to define the L dependence of Cu-lines under high current stress. This includes electron flow dependency to explain line and via depletion effects for void formations under various stress conditions. We report a non-linearity in the L dependence on the jL product and a slight temperature dependence on the Blech Threshold (jL)c.

While the self-learning kinetic Monte Carlo (SLKMC) method enables the calculation of transition rates from a realistic potential, implementations of it were usually limited to one specific surface orientation. An example is the fcc (111) surface in Latz et al. 2012, J. Phys.: Condens. Matter 24, 485005. This work provides an extension by means of detecting the local orientation, and thus allows for the accurate simulation of arbitrarily shaped surfaces. We applied the model to the diffusion of Ag monolayer islands and voids on a Ag(111) and Ag(001) surface, as well as the relaxation of a three-dimensional spherical particle.

In this work, a novel low dielectric constant (low-k) pore sealing approach was engineered by depositing firstly a sub-2 nm SAMs and then a 3 nm TiN barrier film. The low-k film was pretreated by plasma to introduce hydroxyl groups onto the surface, followed by SAMs deposition. Then a TiN film was deposited from tetrakis(dimethylamino)titanium (TDMAT) via ALD as a dielectric barrier. Penetration of Ti atoms into low-k was measured and used to evaluate the sealing ability of SAMs. For the samples covered with SAMs, around 90% reduction of Ti atoms penetration was achieved. The pore radius was reduced to below 0.5 nm after the barrier deposition. The ∆k after pretreatment and after SAMs are 0.1 and 0.16, respectively.

Carbon nanotubes (CNTs) have been considered as a promising interconnect material to replace the solder bump used in the flip chip package because of their special electrical, mechanical and thermal properties, which may promote both the performance and reliability of the flip chip packaging. In this paper, electrophoretic deposition (EPD) of CNTs on substrates has been demonstrated for the interconnect application. EPD is a simple, low cost and high throughput process that is capable to produce densely packed film with good homogeneity at low temperature. By altering the electric fields and deposition time during the EPD process, the thickness of the CNTs film could be controlled. In this study, multi-walled carbon nanotubes (MWCNTs) were successfully coated on the various substrates using the EPD method. A highly uniform CNTs microstructure film with thickness over 5 µm was achieved. In addition, the selective depositions of CNTs on the pre-defined bond pads to form CNTs bumps were also accomplished. By employing typical flip-chip bonding technique, high density CNTs bumps were aligned to form a test chip/host substrate interconnects. The electrical conductivity of the CNTs interconnects was carried out using four-point probe measurement. Reliable electrical contacts with linear relationship in the current-voltage (I-V) characteristic suggesting ohmic behaviour were attained. The overall resistances extracted were also relatively low. These superior electrical properties have demonstrated that the CNTs bumps deposited using EPD method is a viable way to serve as an alternative to current metal solder interconnects material such as Sn-Pb alloys. Hence, it offers a promising interconnect application in the quest for device miniaturization in microelectronic industry.

Horizontal carbon nanotube (CNT) interconnects are fabricated using a novel integration scheme yielding record wall densities >1013 shell/cm2, i.e. close to the density required for implementation in advanced integrated circuits. The CNTs are grown vertically from individual via structure and subsequently flipped onto the horizontal wafer surface. Various electrode designs are then used to produce different geometries of metal-to-tube contact such as side contact or end contact. CNT lines - 50 to 100 nm wide and up to 20 µm long - are realized and electrically characterized. The sum of the contact resistances from both ends of the lines is close to 500 Ω for 100 nm diameter lines which leads to a specific contact resistance of 1.6 10-8 Ω.cm2 per tube. With the developed technology, post-annealing of the contact does not improve the resistance values. Both chromium and palladium are used as contact metal. While contact resistance is equivalent with the two metals, the resistance per unit length of the lines does change and is better with palladium. This dependence is explained using a tunnelling model which shows that statistics of individual tube-metal contact is required to properly model the electrical results. Direct experimental evidences showing that only a part of the CNTs in the bundle is electrically connected are also given. Our best line resistivity achieved is 1.6mΩ.cm which is among the best results published for horizontally aligned CNTs and the only one with a realistic geometry for future VLSI interconnects.

Power consumption and dissipation during electrical operation lead to a temperature rise in the package. Elevated temperature in the package structure induces thermo-mechanical stresses which may increase reliability risks. Robust and reliable package design for power systems requires comprehensive analysis of system electrical, thermal, and mechanical behavior. This paper presents a self-consistent approach for package reliability analysis with coupled electro-thermal and thermo-mechanical modeling using TCAD tools.

Scaling effects on Cu microstructure, resistivity, dielectric materials, and electromigration (EM) and time dependent dielectric break down (TDDB) reliabilities for Cu interconnects were reviewed. A simple empirical model of Cu resistivity related to Cu line area was presented. Cu line microstructures containing small grains mixed with large bamboo grains in Cu damascene lines from technology nodes below 65 nm were observed. As predicted in previous work, the EM lifetime was found to degrade by about 50% for every new generation even for the same current density. The Cu grain size was found to have a large impact on pure Cu and Cu alloy EM lifetime and activation energy Ea. Ea for pure Cu line capped with selective electroless CoWP on near-bamboo, bamboo-polycrystalline, to polycrystalline only line grain structures was reduced from 2.2 eV to 1.7 eV to 0.75 eV, respectively. Ea for 40 nm wide bamboo-polycrystalline lines capped with selective chemical vapor deposition (CVD) Co was found to be 1.7 eV. Using pure Cu and Cu(Al) or Cu(Mn) diluted impurity seed layers in 40 nm wide, bamboo-polycrystalline microstructure lines and above 100 nm wide, near bamboo-like grained lines, Cu-alloy lines enhanced EM lifetimes and increased QEM from 0.9 to 1. eV and 1.0 to 1.2 eV, respectively, compared to pure Cu lines. Inter-level TDDB testing on vias connecting M1 to M2 with a via chamfer angle that varied from 58o to 81o have very similar performance with intra-level M2 data with no vias tested at the same field. This result combined with the data from a separate study, which allowed the chamfer path to be isolated from the M2-level path, suggested that the failure took place preferentially along the weak cap/ILD interface at M2 and not at the via chamfer. TDDB acceleration data indicated that the root E model was overly conservative and a more aggressive model provided a better fit to the data. TDDB lifetimes correlated fairly well with the percentage of porosity in the dielectric materials.

Low-k dielectric films can be substantially damaged during plasma processing. High energy UV and VUV photons emitted by plasma play the key role in damaging the porous low-k films directly or indirectly by stimulating chemical reactions with radicals in plasma and plasma afterglow. The different ULK samples (k: 2.0-2.2, porosity: 30-50%, pore radius: 1-2 nm) were studied by exposing to five radiation sources at various wavelengths (VUV: 193 nm, 147 nm, 104-106 nm, 58.3 nm, and EUV: 13.5 nm). Time-spatial behavior of the ULK damage as a function of photons fluence was studied by FTIR spectroscopy and XRF analysis. It is shown that the degree of damage depends on wavelength of UV light. The major UV damage was observed at the wavelengths below 193 nm. The maximum damage corresponds to 147 nm while the degree of damage at 58.3 nm was much smaller. In the case of organosilicate (OSG) based ULK materials, the degree of damage, as a rule, increases with porosity. Organic low-k materials are damaged more than OSG at 193 nm, but at shorter wavelengths (147, 106, 58.3 and 13.5 nm) they are more stable than OSG. One-dimensional model for radiation absorption and dynamics of CH3 group destruction in ULK films was developed. The cross-sections of photons absorption and photo-stimulated Si-CH3 bond breaking in ULK films for 13.5 -147 nm wavelength range were derived from a combined experimental and modeling study. The obtained values allow to simulate the VUV/EUV induced modifications of low-k materials with different composition, to understand better the mechanisms of plasma damage and to generate ideas for controllable modifications of low-k materials.

This study demonstrates that thin metallic oxide layers, such as OsOx and ZnO, function as a strong adhesion layer between Cu film and glass substrate. The adhesion strength was studied with a micro-scratch tester and the films and interfaces were characterized by energydispersive X-ray spectrometry. The presence of an extremely thin intermixing layer was confirmed at the metal/glass interfaces. The formation of such an interfacial layer increased the adhesion strength significantly.

Wireless communications such as those in cell phones are utilizing increasing chip design complexity. For example analog mixed-signal chips can contain RF capability which requires integrated inductors [1,2]. High performance RF designs are enabled by the use of thick Copper (Cu) and Aluminum (Al) wires (>3um). In particular, the quality factor of the inductor, which is the ratio of magnetic stored energy over average dissipation, is dependent on the metal thickness. High quality factors, can be achieved by using thick Cu inductors. In some applications, the total thickness of Cu in the inductor can be as much as 12 um.

The fabrication of thick Cu layers is in many ways easier than that of thin Cu layers. For example, there are no limitations in terms of lithography or liner and seed layer thickness. However, there are still challenges with fabrication due to stress. Cracking of the dielectric can occur, due to the mismatch in coefficient of thermal expansion between Cu and SiO2, and due to the thick Cu layers in the inductor stack. Both the layout and the processing must be optimized to ensure that cracking does not occur.

This paper will discuss current applications, inductor design, and the reliability challenges and solutions associated with thick Cu interconnects.

Pore sealing has become a critical issue for the implementation of porous low-k dielectrics and for realizing acceptable reliability performance of the interconnect. This study focuses on fabrication of ultra-thin, conformal and plasma resistant pore seal layer and on understanding parameters playing a role in sealing the surfaces of porous low-k films. It was found that 2.5 nm-thick pore seal layer shows a perfect toluene seal property for the porous low-k film whose pore radius is 1.48 nm. The pore seal layer still show a good toluene seal property after irradiation of He plasma at 250°C for 10 sec. The increments of dielectric constant by applying the pore seal layer and by the He plasma irradiation for 10 sec are 0.04 and 0.03, respectively. Interestingly, all of toluene seal property, refractive index of the bottom part of the film and dielectric constant started to deteriorate after irradiation of He plasma for 20 sec. It was suggested that when toluene seal property degrades, plasma would start diffusing into pores and both refractive index of the bottom part of the film and k value start to increase.

Under the FP7 HELIOS project a 16 channel 10G transceiver based on a separate integrated transmitter incorporating hybrid lasers and modulators on silicon and a separate receiver both for 1550nm wavelength range has been demonstrated. An MZM (ITLMZ) chip consisting of a single mode hybrid III-V/silicon laser, a silicon Mach-Zehnder (MZ) modulator and an optical output coupler exhibited 10G operation with high BER. A 200GHz 16 channel receiver with polarization management was obtained with a 2D grating coupler, 2xAWGs and 16 Ge photodiodes. Polarization Dispersion Loss (PDL) was below 1dB, Bandwidth (BW) above 20GHz, receiver sensitivity in the order of 0.08 A/W

This paper describes an alternate two-step metallization scheme for porous dielectrics. The patterned dielectric surface is first treated in a plasma etch chamber where the dielectric surface is coated with a very thin carbon-based film. This is followed by electroless copper deposition. The plasma post-etch treatment (PET) film seals the pores of the dielectric, minimizes dielectric damage, and functionalizes the dielectric to enable electroless plating.

Package-induced failures for BEOL interconnects in sub-45nm technology nodes have drawn attention to the great silicon and packaging integration challenges introduced by the weak mechanical properties of ULK-containing metallization elements. Empirical data and modeling studies for a range of silicon and packaging factors at 20nm node reveal fundamental insights into susceptibility to damage and approaches for recovery. Analysis of increase in degradation as BEOL layouts evolve to finer dimensions points to understanding of changes that will enable continued device scaling.

In this paper we demonstrate an add/drop filter based on SiC technology. Tailoring of the channel bandwidth and wavelength is experimentally demonstrated. The concept is extended to implement a 1 by 4 wavelength division multiplexer in the visible range.The add/drop filter consists of a p-i'(a-SiC:H)-n/p-i(a-Si:H)-n photodetector with two front and back optical gates. Tailoring the filter wavelength is achieved by applying a 400 nm background and changing front and back biased optical gates. Results show that, front background enhances the light-to-dark sensitivity of the long and medium wavelength channels and quench strongly the others. Back violet background has the opposite behavior; it enhances channel magnitude in short wavelength range and reduces it in the long ones. This nonlinearity provides the possibility for selective removal or addition of wavelengths. An optoeletronic model gives insight on the system physics and explains the light filtering properties of the add/drop filter.

Wafer level metal bonding involving copper material is widely used to achieve 3D functional integration of ICs and ensure effective packaging sealing for various applications. In this paper we focus on thermocompression bonding technology where temperature and pressure are used in parallel to assist the bonding process. More specifically a broad range of conditions was explored and interesting results were observed and are reported. Indeed, despite a relatively high roughness, the presence of a native oxide and the lack of surface preparation, there still exists a process window where wafer level bonding is allowed. In these conditions, limiting the bonding mechanisms to basic copper diffusion is no longer satisfactory. In this study, a specific scenario inspired by both wafer bonding and metal welding state of the art is put forward. Accordingly, pure copper diffusion through the bonding interface is lined with plastic deformation and metallic oxide fracture. In addition, polycrystalline film deformation due to thermomechanical stress is highlighted and grain growth and voiding formation are observed and confirmed.