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Published online by Cambridge University Press: 29 May 2013
Package-induced failures for BEOL interconnects in sub-45nm technology nodes have drawn attention to the great silicon and packaging integration challenges introduced by the weak mechanical properties of ULK-containing metallization elements. Empirical data and modeling studies for a range of silicon and packaging factors at 20nm node reveal fundamental insights into susceptibility to damage and approaches for recovery. Analysis of increase in degradation as BEOL layouts evolve to finer dimensions points to understanding of changes that will enable continued device scaling.