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Understanding the Fundamentals for Package Induced Failure in BEOL Interconnect at 20nm Node

Published online by Cambridge University Press:  29 May 2013

Vivian Ryan ,
Shan Gao ,
Chirag Shah ,
Holm Geisler ,
Dirk Breuer ,
Frank Kuechenmeister ,
Jens Paul ,
Zafer Kutlu ,
Kashi Vishwanath Machani  and
Matthias U. Lehr
Vivian Ryan
Affiliation:
GLOBALFOUNDRIES Inc., 257 Fuller Road, Albany, NY 12203, USA
Shan Gao
Affiliation:
GLOBALFOUNDRIES Inc., 400 Stone Break Rd Ext, Malta, NY 12020, USA
Chirag Shah
Affiliation:
GLOBALFOUNDRIES Inc., 1050 E Arques Ave, Sunnyvale, CA 94085, USA
Jens Paul
Affiliation:
GLOBALFOUNDRIES Inc., Wilschdorfer Landstrasse 101, 01109 Dresden, Germany
Zafer Kutlu
Affiliation:
GLOBALFOUNDRIES Inc., 1050 E Arques Ave, Sunnyvale, CA 94085, USA
Matthias U. Lehr
Affiliation:
GLOBALFOUNDRIES Inc., Wilschdorfer Landstrasse 101, 01109 Dresden, Germany
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Abstract

Package-induced failures for BEOL interconnects in sub-45nm technology nodes have drawn attention to the great silicon and packaging integration challenges introduced by the weak mechanical properties of ULK-containing metallization elements. Empirical data and modeling studies for a range of silicon and packaging factors at 20nm node reveal fundamental insights into susceptibility to damage and approaches for recovery. Analysis of increase in degradation as BEOL layouts evolve to finer dimensions points to understanding of changes that will enable continued device scaling.

Keywords

microelectronicsdielectric propertiesthermal stresses
Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 1559: Symposium AA – Advanced Interconnects for Micro- and Nanoelectronics—Materials, Processes and Reliability , 2013 , mrss13-1559-aa08-01
Copyright
Copyright © Materials Research Society 2013 

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References

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