The dielectric quality (defect density, Do and breakdown strength, Fbd) of 150Å SiO2 gate oxide (GOX) films grown by conventional or stacked oxidation scheme are discussed from the leakage measurements of polysilicon capacitors on test structure simulating our submicron CMOS process. Various polysilicon (poly) deposition processes from silane pyrolysis (570°C -620°C) were used by the low pressure chemical vapor deposition (LPCVD) technique. Both in situ and ex situ poly doping by phosphorus (P) were used to ascertain their impact on the GOX properties. The substructural characteristics of the poly/SiO2 and SiO2/Si interfaces generated by various combinations of GOX and poly deposition processes were done by the high resolution TEM lattice fringe technique under phase contrast mode.

Thin layers of oxides (10–11nm) were fabricated by rapid thermal (RTP) or furnace oxidation. The RTP oxides were grown at different temperatures and were exposed to a two step post oxidation anneal (POA). The furnace oxides were grown at one temperature and received different POA/s. As gate metallization, in-situ phosphorus-doped polysilicon was used. Post poly anneal (PPA) is carried out in the RTP system using a set of temperatures. After having defined MOS structures by photolithography oxide charges, breakdown voltages and breakdown charges were determined. For different current densities, FN-voltage shift during constant current injection was monitored to make lifetime predictions. Received data were correlated to the different process parameters.

A low thermal budget process is demonstrated for the fabrication of submicron Boron doped polysilicon gate p-channel MOS devices with ultra thin gate insulators. All critical processing steps with temperatures above 700 °C, including gate oxide growth and shallow source/drain junction formation, were performed by Rapid Thermal Processing (RTP). In situ doped polysilicon was used to eliminate the need for a high temperature drive-in step. Surface channel p-channel enhancement mode devices with excellent characteristics were fabricated to demonstrate the feasibility of this process.

A polysilicon gate structure for application as gate material in p-channel JFET's is presented. The structure was manufactured using solid-phase epitaxy of an evaporated antimony/amorphous—silicon layer. The fabrication process together with experimental evaluation of both diode and JFET characteristics is given. The structure shows near ideal n+p-junction behaviour and the fabricated JFET's are normally off with good values of subthreshold swing and transconductance.

Polysilicon gates are an important element of modem MOS integrated circuit technology. The workfunction difference (ϕps) between the polysilicon gate and the silicon substrate is a vital parameter of the MOS system because it determines the threshold voltage of the field-effect transistor. Ideally, ϕps is determined by the doping level in both polysilicon and the substrate. In reality process variations influence the ϕPS in a tangible way. Some of these effects are reviewed in the present paper.

Prior to growth of polyoxide, amorphous-Si with a cap of low temperature oxide was annealed to improve the dielectric property of polyoxide. Current-electric field, critical electric field, critical electric field histogram, and Fowler-Nordheim conduction plot were evaluated. The interface of polyoxide and poly-Si was observed with a transmission electron microscope. The annealing of the amorphous-Si prior to oxidation was effective to improve the dielectric property of the polyoxide.

Time dependent dielectric breakdown (TDDB) characteristics and TEM observation of ultra-thin silicon dioxide with the polysilicon gate after post-annealing and oxidation at 1000-1100 °C are discussed. The high temperature post-annealing decreases the TDDB characteristics of ultra-thin oxide with polysilicon gate. The charge to breakdown is reduced drastically with increasing the annealing temperature and annealing time. The dielectric breakdown reliability degradation of ultra-thin tunneling oxide by the post-annealing can be explained as the partial oxide thinning and electric field concentration due to the increase of roughness at the polysilicon gate/ultra-thin tunneling oxide interface. This increase of roughness is due to the grain growth of polysilicon gate and viscous flow of oxide, which are enhanced with increasing the annealing temperature and time.

In this paper we report on the quality of gate oxides obtained using three different oxidation techniques, namely thermal oxidation, rapid thermal oxidation and stacked gate oxidation. We report on the oxide thicknesses, the flatband voltage, threshold voltage, and QSS/Q values for MOS capacitors fabricated using these three techniques. We also fabricated MOSFET's using thermal oxides and stacked gate oxides, and find that the stacked gate oxides have a lower gate oxide defect density. Lattice images have also been obtained for the Si/SiO2 interface using transmission electron microscopy (TEM). We find that stacked oxide synthesis results in lower stresses and asperities at the interface relative to thermal and rapid thermal oxidation.

Polysilicon thin film transistors are now in mass production. Key factors of the success are thinner polysilicon film and thermal oxidation. Practical applications of polysilicon thin film transistors have been limited, however, because of high temperature processing. Alternative technologies to thermal oxidation are very low pressure deposition, solid-phase crystallization, laser-annealing and hydrogenation. These technologies are compatible with low temperature processing and will contribute to the advance of polysilicon thin film transistors in the future.

Hydrogen diffusion in as-deposited and in oxidation-annealed polycrystalline silicon films was investigated using n-type accumulation-mode MOSFET's. The diffusion was studied by measuring the reduction in the grain boundary trap density with hydrogenation time. The number of traps in fully hydrogenated as-deposited films fell to about 45% of the initial trap state density and fell to about 20% in the oxidized-annealed films. Concurrently, the mobility increased about 95 % to 5cm2/Vs in the as-deposited films and by about 55 % to 25 cm2/Vs in the oxidized polysilicon devices. The effective preexponential diffusion coefficient and activation energy for hydrogen diffusion in the two different films were Do= 5.4×10−10 cm2/s and EA= 0.37 eV for the as-deposited polysilicon and Do=2.1×10−10 cm2/s and EA= 0.36 eV for the oxidized polysilicon.

We report activation energy measurements of the source-drain current of polysilicon thin film transistors (TFTs). We have shown earlier that measurements carried out on unhydrogenated TFTs can be explained by the presence of band tail states in addition to deep localized states. After hydrogenation, the density of band tail states is greatly reduced and the data can be fitted with only the deep states.

In the present work we have studied both n and p channel TFTs. This was done by measuring both type of devices on the same wafer so that differences due to processing conditions could be ruled out. Both type of devices had intentionally undoped channels and were identical except for the n or p type source-drain regions. The thinner TFTs discussed in this work have a sharper drop in the activation energy than would be expected from idealized calculations. This sharp drop in activation energy is also an indication of a sharp subthreshold slope. This decrease in subthreshold slope (Volts/decade) is due to the complete depletion of the channel polysilicon, which leads to a rapid increase (or decrease) in the surface potential as a function of the gate voltage.

The effects of hydrogen plasma passivation on n-channel polycrystalline silicon thin film transistors fabricated with a maximum temperature of 600°C are investigated. It is found that charge, sharing, avalanche multiplication, grain size, and gate edge in-situ passivation or even partial hydrogenation can all contribute to the small geometry effect. At low drain bias, the channel charges supported by the source and drain fringing fields cause threshold shifts for short channel devices; at high drain bias avalanche multiplication is the dominant effect. The charge sharing effect may be related to the unpassivated trap-states in the channel since thresholds of fully hydrogenated devices became independent of channel length at low drain bias. The threshold shifts of narrow width devices were also diminished with increasing hydrogenation time. An anomalous turnaround effect of the field effect mobility in saturation regime for the short channel devices is observed near saturated hydrogenation. This effect is probably due to the passivation of back-channel defects and the reduction in impact ionization rate by hydrogenation. Saturated hydrogenation not only improves device performance but also reduces small geometry effects. Avalanche multiplication remains the dominant mechanism for short channel effect in the saturated hydrogenated devices.

The effect of gate dielectric on the electrical characteristics of n-channel polysilicon thin film transistors was investigated. The following insulators were studied: silicon dioxide grown by wet oxidation, silicon dioxide deposited by plasma enhanced chemical vapor deposition (PECVD) and nitrogen-rich silicon nitride deposited by PECVD. It was observed that the effective electron mobility in TFTs having a deposited dielectric, either silicon nitride or silicon dioxide was higher than that measured in devices with grown silicon dioxide. The TFT leakage current was found to be lowest in devices with PECVD silicon nitride. Devices with deposited dielectrics did not degrade after a positive gate bias stress. However, reduction of the threshold voltage was observed in devices with PECVD silicon nitride, when they were subjected to a negative gate bias stress.

Polysilicon TFTs and TFT-CMOS circuits are characterized. Circuit elements examined comprise subcircuits pertinent to integrated drivers suitable for flat panel display applications. Performance features of multistage static row drivers are also presented. Additionally, AC measurement of TFTs was performed in order to extract device parameters. The channel mobility measured in a time of flight environment is presented and discussed.

We report on the characteristics of polycrystalline silicon (polysilicon) thin film transistors (TFTs) fabricated with low temperature crystallized LPCVD amorphous silicon film as an active layer and plasma enhanced chemical vapor deposition (PECVD) SiO2 as a gate insulator. High performance transistor characteristics are achieved, even though no process temperature exceeds 600°C. No threshold drift has been observed. As a result, these devices are highly suitable for application to image scanners as well as flat panel displays.

A new process architecture for fabricating CMOS thin film transistors (TFTs) using in-situ-doped polysilicon source-drain layers is proposed. In the new architecture, a top-gate n-channel TFT and a bottom-gate p-channel TFT, or vice versa, form a CMOS pair. This allows an n+ - doped polysilicon bottom (or top) layer to serve simultaneously as the source-drain layer of the n-channel TFTs and the gate layer of the p-channel TFTs; while a p+ - doped polysilicon top (or bottom) layer serves as the source-drain layer of the p-channel TFT and the gate layer of the n-channel TFT. It thus eliminates the deposition of a separate doped gate layer normally required in the conventional process flow. In addition, a thin tri-layer stack, consisting of undoped-poly / gate dielectric / undoped-poly, separates the two doped polysilicon layers, thus allowing the use of a single island mask to define the channel regions for both the n- and p-channel TFTs. As a result, the photolithographic steps are also reduced by one mask. Working n- and p-channel TFTs with both top- and bottomgate structures, obtained by reversing the dopant types of the top and the bottom layers, have been successfully demonstrated using low-temperature (< 600 °C) polysilicon technology.

Polysilicon TFT characteristics are shown to be dependent on the nature of the polysilicon film used as well as the TFT fabrication process. Best results were obtained when silicon self-implant and regrowth techniques were used together with plasma hydrogenation. TFTs exhibiting a mobility of 115 cm2/V-sec, subthreshold slope of 0.27 V/decade, leakage current below 0.01 pA/μ;m, and an on-off ratio of 10 orders of magnitude have been fabricated.

An improved polysilicon high voltage thin film transistor (HVTFT) structure with field-plate-controlled offset region (FP-HVTFT) is proposed for eliminating the current-pinching phenomena often observed in the conventional offset-gate polysilicon HVTFTs. The new metal field plate serves, in lieu of ion implantation, to control the conductivity of the offset region. By properly biasing the field plate to distribute the drain electric field at both ends of the offset region, high-voltage operation of up to 100 V, suitable for many large-area applications, is achieved. Good turn-on characteristics without current-pinching effects are consistently obtained. Moreover, the new FP-HVTFT also eliminates the lightly-doped-drain implant normally required in conventional offset-gate HVTFTs, resulting in a simpler and more reproducible process flow.

Carrier transport in the channel region of polysilicon thin film MOSFETs is affected by the presence of grain boundary potential barriers and is further complicated by the modulation of the grain boundary barrier height with gate voltage. Passivation of the trap sites with atomic hydrogen reduces the barrier height and thereby improves the performance of polysilicon transistors. In this paper, we demonstrate the effectiveness of Rapid Thermal Annealing (RTA) using Si3N4 as a solid source of H as a passivation technique for both inversion and accumulation mode polysilicon MOSFETs. ON/OFF ratios of 107 can be obtained by RTA passivation for inversion mode polysilicon MOSFETs compared to 106 after furnace passivation permitting the potential application of these MOSFETs both as load transistors in SRAMs as well as pass transistors in DRAMs. In contrast, the ON&OFF ratio of accumulation mode polysilicon MOSFETs does not show any improvement even though ID and VT improve with passivation. This is because of excessive back channel leakage in accumulation mode MOSFETs which increases with passivation.