The many advantages of polycrystalline Si (poly-Si) to semiconductor device manufacturing are reviewed, together with methods of deposition and new uses.

A LPCVD polysilicon deposition with in-situ anhydrous HF cleaning process has been developed. The deposited polysilicon and interface properties have been characterized using SIMS, XTEM, RBS, and Auger analysis. The results indicate that an interface oxide free polysilicon deposition using conventional LPCVD furnace can be achieved by careful design of in-situ anhydrous HF cleaning process. After short time rapid thermal annealing, random and channel RBS studies show that most of the deposited polysilicon is epitaxially aligned with silicon substrate and there is no oxide ball up phenomenon. Twinning structure was observed under TEM. No impurity segregation at the poly-mono silicon interface confirms that the interface is oxide free. Possible applications of this polysilicon process include polysilicon emitter contact for high speed bipolar technology and source/drain contacts for MOS devices.

The effects of using tertiarybutylphosphine (TBP) as a source of phosphorus dopants during polycrystalline silicon (polysilicon) deposition in a rapid thermal processor (RTP) was investigated using TEM, SIMS, spectrophotometry, and 4-point probe analysis. It was found that the introduction ot TBP significantly inhibited the deposition of polysilicon on silicon dioxide, but only slightly reduced the growth rate of polysilicon on polysilicon. The introduction of TBP during the last 20% of the deposition time formed a thin phosphorus-rich layer on the top surface. Adsorption of the phosphorus was found to be gas-transport-limited. Incorporation of the dopant into the rest of the polysilicon layer was accomplished with an in-situ anneal (RTA) in nitrogen, resulting in a resistivity as low as 720 μΩ-cm.

The grain size of the polysilicon was found to increase with deposition temperature, however was not affected by the introduction of the dopant, or any subsequent anneal. It ispostulated that unincorporated phosphorus, and oxygen and carbon in the grain boundariesprevent the combination and growth of silicon crystals.

Rapid Thermal Chemical Vapor Deposition (RTCVD) of undoped and insitu doped polycrystalline silicon films has been accomplished in a cold-wall reactor. Dichlorosilane was used for the silicon source and AsH3 gas was used as the dopant source. Thedeposition kinetics of poly-silicon films on silicon dioxide over a range of deposition temperatures, pressures and carrier gas chemistries was studied. Both blanket and selective deposition modes were examined. The poly-silicon films were examined by scanning electron microscopy (SEM) and transmission electron microscopy (TEM) for morphology and grain size analysis. Using X-ray diffraction technique, preferred grain orientation dependency of poly-silicon films on growth conditions was investigated. Dopant incorporation, dopant activation and oxygen content of polysilicon films were measured by secondary ion mass spectrometry (SIMS), four point probe, and spreading resistance profiling (SRP) techniques.

This paper is to report the results of material characterization of polysilicon films deposited by RTCVD, and to address the applications and advantages of ‘Integrated Processing’ technology involving deposition of polysilicon.

Low pressure chemical vapor deposition of polysilicon in a lamp heated rapid thermal processor (RTCVD) has been studied. Polysilicon films were deposited using SiH4 diluted in Ar. Structural characterization of the films was accomplished by transmissionelectron microscopy (TEM), scanning tunneling microscopy (STM), secondary ion mass spectroscopy (SIMS), auger electron spectroscopy (AES) and ultraviolet surface reflectance measurements. Smooth polysilicon films were obtained at deposition temperatures above 700ºC with rms roughness values better than 100 Å. Both p- and n- polysilicon gated MOS capacitors were fabricated using 80 - 200 Å thick gate oxides grown by dry oxidation in a conventional furnace. Polysilicon doping was achieved by ion-implantation and rapid thermal annealing (RTA). Our results show that the electrical properties ofthe capacitors fabricated using RTCVD polysilicon are comparable to those of conventional polysilicon. Dopant diffusion through the gate is a problem for both types of polysilicon and can lead to a degradation of the electrical properties.

Rapid thermal LMVD has been applied to the deposition of polysiliccn layers. The single process wafer sits in an air—cooled quartz chamber, and is heated by tungsten—halcgen lamps. A nicrowave cavity upstrean of the hot zone may be used to introduce a remote plasma.

Pblysilicon films have been deposited on ocidized suhstrates in the temperature range 590C–860C, and at pressures between 0.lmber and 10mbar. Conditions for the reduction of carbon and oxygen levels down to 5x1017 cm are presented.

An in—situ CF4 plasma clean prior to polysiliccn deposition is shown to dramatically affect grain—size. At 720C and Imbar, plasma-cleaned polysilicon has a grain—size of 35Chm, whereas non—cleaned polysilicon has a grain—size of only 120nm. The CF4 schedule leaves a clean ocide surface with fewer nucleation sites, resulting in larger grains.

Both types of polysilicon were used in the fabrication of TMT'S. Devices with larger grain material pass 10 times as much current as those with smaller grains, show a channel nobility of >20cm v s, and have a threshold voltage of 5V. Thus, direct deposition of polysilicon layers on a plasma—cleaned substrate is an attractive alternative to crystallization from amorphous silicon, for TFT's.

The deposition of in situ phosphorus doped silicon films was performed using disilane (Si2H6) instead of monosilane (SiH4) as the silicon source gas. The negative aspects of in situ doping with phosphine, namely low deposition rates and poor across wafer uniformity, were to a large extent eliminated. Haze-free polycrystalline films were deposited at ∼60 Å-min1 with less than 5% radial thickness variation over a 100 mm wafer. However, the temperature suitable for depositing films using Si2H6 was shifted downward from that used for SiH4 and similarly, the conditions for good quality (haze-free)films were adjusted. Within specific temperature ranges, varying the gas pressure, flow,and Si2H6 to PH3 ratio resulted in the formation of oneof three types of haze. The films produced had unusually low resistivities of ∼770 μohm-cm after furnace annealing at 850ºC for 1800s. A 20 nm thick surface layer of amorphous silicon oxide was revealed during transmission electron microscopy (TEM) examination of annealed films. Although this oxide layer was undoped, the phosphorus gradient, measured by energy dispersive x-ray analysis (EDX) and secondary ion mass spectroscopy (SIMS), increased towards the surface of the polycrystalline film, suggesting that dopant was diffusing to the surface. A matrix involving different annealing and capping layers was conducted to investigate this phenomenon further. Extremely large grains resulted when a capping layer of SiO2 was deposited prior to rapid thermalannealing (RTA). An autodoping effect was observed when another capping layer, such as undoped polycrystalline silicon, was used.

To develop the EPR material quality, electrical and structural charact erizations were executed by EBIC, LBIC, TEM, ECP and X diffraction. Two interface types were observed; some interfaces parallel and constitued by Σ3 and Σ9 twins, show low electrical activity; other are curved with no defined index and higher electrical activity. Some orientations such as (111),(220),(331) appear more frequently.

The thermal stability of Co silicide on single crystal and polycrystalline Si has been investigated. Co films were evaporated onto (100) Si and undoped polycrystalline Si and annealed in vacuum. Resulting silicide films were examined using Rutherford backscattering spectroscopy, scanning electron microscopy, electron—induced x—ray spectroscopy, and sheet resistivity measurements. We find that CoSi2 on single crystal (100) Si remains stable through 1000ºC. In contact with undoped polycrystalline Si, intermixing begins at temperatures as low as 650ºC for 30min annealing. The Co silicide and Si layers are intermixed after 750ºC 30min annealing, giving islands of Si surrounded by silicide material, with both components extending from the surface down to the underlying oxide layer. The behavior of CoSi2 contrasts with results reported for TiSi2 which agglomerates on single crystal Si around 900ºC but is stable on polycrystalline silicon as high as 800ºC. Resistivity measurements show that the Co silicide remained interconnected despite massive incursion by Si into the silicide layer.

TiSi2 thin films were formed on crystalline and amorphous silicon substrates obtained by Ge+ and Ge++B+ implantation and optional subsequent annealing. Transmission electron microscopy, X-ray diffraction and electrical resistivity analysis revealed that the silicide formed on amorphous Si has more tendency to have a C54 structure rather than the metastable C49 structure. Also, the grain size is smaller and the silicide/silicon interface is smoother for silicides formed on amorphous Si. Comparison between implanted and unimplanted, (100) and (111) Si substrates indicated that the origin of the differences can be attributed to the latent energy stored in amorphous silicon, which favors the silicide with fine grains and promotes the transformation to the C54 phase. Non-random distribution of planar defects in C49 grains has been observed by plan-view TEM. A proposal that these defects are transformation stress induced microtwins is presented.

The geometrical shape and the thermal stability of the TiSi2/poly-Si interface on narrow lines has been studied. The examined line-widths varied between 0.8 μm and 1.5 μm. The thermal stability was found to strongly correlate to theactual line-width of the structures. At the onset of degradation, at and above 900 ºC, narrow lines were observed to disintegrate at a much faster rate than wider ones. Cross-sectional microscopy (TEM and SEM) revealed the TiSi2/poly-Si interface to be curved inwards. The interface bowing was found to be more pronounced on narrow lines. It is suggested that the interface bowing results from a mechanical pinning of the TiSi2/poly-Si interface by the side-wall spacers.

Titanium silicide (TiSix), used as polycide gate consists of TiSi1.1 and amorphous silicon (a—Si), was deposited by Plasma Enhanced Chemical Vapor Deposition method (PE—CVD). The effect of a—Si layer in PE—CVD Ti polycide gate dielectrics has been studied. In order to evaluate the a—Si layer effect, three types of samples were prepared on gate SiO2 film with following structures: a) a—Si / TiSil.1 / a—Si / phosphorus (P) doped poly—Si, b) a—Si / TiSi1.1 / non—doped poly—Si / P doped poly—Si and c) a—Si / TiSi1.1 / P doped poly—Si, respectively. Furthermore, in order to avoid the influence of native oxide existence at the interface, the pre—cleaning treatment was performed in—situ on the poly—Si film surface before TiSi1.1 film deposition. The gate dielectric strengths of these samples indicate that the gate dielectric degradation in PE—CVD Ti polycide gate is greatly dependent on Si under layer crystallization. It is effective using a—Si film as the under layer in decreasing the gate dielectric degradation. This is due to the Ti oxide interlayer, formed at the interface of TiSi2.0 and poly—Si films, whichrestrains the TiSix local penetration.

The concept of using cobalt disilicide as a self-aligned metallization scheme for gate/interconnection and contact formation is gaining wide acceptance. The silicide formation on the gate will require a Co-metal film interaction with the underlying polysilicon that may be doped heavily. We have investigated the silicide formation kinetics during this reaction. The effect of different dopants (B,P, and As) and their concentration on the Co-Si interaction and the dopant redistribution during such reactions were investigated. The results from these studies will be presented and discussed.

The presence of a thin (10-30Å) oxide (“native oxide”) layer on a silicon surface prior to the deposition of another film on that surface can contribute todifficulties with subsequent device processing steps, e.g. contact metallization and hightemperature annealing or oxidation. Thus, the in situ process capability of “native oxide” removal affords an advantage over the conventional method of aqueous hydrofluoric acid cleaning prior to a film deposition step. This study describes such a technique, in which an in situ pre-deposition clean with C2F6 gas, using reactive ion etching (RIE) prior to tungsten silicide deposition, is employed. This technique allows post-silicide deposition high-temperature heat treatment and wet oxidation without loss of film adhesion or other obvious degradative effects. We also report the useof Secondary Ion Mass Spectrometry (SIMS) to show that this procedure has een effective in the removal of the oxide layer prior to silicide deposition. This study includes definition of the RIE etch parameters which provide acceptable etch selectivity of the oxideto silicon, and avoidance of excessive fluoropolymer formation on the silicon surface.

Rapid thermal annealed (RTA) bilayers of TiW/Ti were evaluated for contact metallization in advanced VLSI Si circuits. It was found that RTA and a minimum thickness of Ti are necessary to achieve consistently low + contact resistance. RTA has little effect on n+ and polysilicon contact resistances. With RTA, TiSi2 is formed at the Ti/Si interface and a thin nitrogen—containing layer is formed on the TiW surface. By controlling RTA temperature and time, the interaction between Si and TiW during RTA could be minimized while the gain factor of p—channel MOSFETs was not degraded. Moreover, the leakage currents of n+ and p+ contact chains did not increase after 30 minute anneals up to 525C.

The mechanism of silicon ion implantation on the crystallization kinetics and the resulting grain sizes of LPCVD α-Si films have been studied by x-ray diffraction and transmission electron microscopy. The solid-phase crystallization was proceeded by random nucleation and growth from the Si/SiO2 interface. The most effective grain size enhancement was found by targeting the peak concentration of implanted siliconbeyond the Si/SiO2 interface, such that the maximum kinetic energy transfer occurred at that interface. The average grain size increases from ∼0.16 μm to ∼2.0 μm by a Si + implantation at 92KeV and a dose of 2X1015 cm-2 for 0.1 μm silicon film. X-ray diffraction intensities were analyzed to optimize implanting dose, beam current and energy for different film thickness. Grain size enhancement was achieved by retarding the random nucleation and increasing the nucleation activation barrier from ∼3.9eV to ∼4.9 eV for the implanted sample. The amorphous to crystalline growth activation barrier of ∼3.2 eV was not altered by Si+ implantation. The observed nucleation and growth kinetics change may be due to the chemical effect of the recoiled oxygen atoms from the substrate. The field-effect mobilities for both n- and p-channel TFTs increase by a factor of two with deep silicon implant.

PECVD a-Si deposited at 250ºC on 7059 glass was used as precursor material to produce low resistivity large grain doped poly Si. The films doped in the range of 1020−1021 cm-3 with P during growth or by ion implantation wereannealed at 700ºC for times 2 to 5 minutes using RTA. A dopant enhanced grain growth was observed with grain sizes of the order of 3 μm for films of only 2000Å thickness. Resistivity as low as 6x10-4 Ω-cm and mobility as highas 34 cm2 /V-sec. were obtained using this low thermal budget process.These values are comparable to those obtained in the literature using significantly higher annealing temperatures.

Significant improvement in properties of polysilicon thin films for VLSI applications was achieved using nanosecond thermal processing causing laser-induced melting followed byrecrystallization. Sheet resistance was reduced by as much as a factor of five on polysilicon thin films and underlying oxide integrity was not detectably disturbed.

The physical processes involved in dopant redistribution during heat treatments of polysilicon layers are described, and one and two—dimensional models based on these are presented. The quantitative effects of the physical parameters determining arsenic andboron distributions in bipolar VLSI emitter—base structures are demonstrated, andclose correspondence shown with available experimental data. Areas needing new models are outlined, and an approach to the modelling of epitaxial alignment is proposed.

Comparative studies of As and B diffusion in polysilicon-on-single-crystal Si systems have been performed by Cross-sectional Transmission Electron Microscopy (XTEM) and Secondary Ion Mass Spectrometry (SIMS). Arsenic and BF2 implanted in 300 nm Low Pressure Chemical Vapor Deposition (LPCVD) polysilicon are diffused into the underlying Si substrate by Rapid Thermal Annealing (RTA) or furnace annealing. Diffusion profiles of Asappear to be continuous across the poly/single crystal Si interface except for a peak at the interface and show a gradual increase towards the interface within the polysilicon layer due to an inhomogeneous distribution of grain sizes in Asimplanted polysilicon layers. On the other hand, indiffusion of B gives a discontinuous doping profile at the interface due to accumulation of B-defect complexes created by dissolution of defectclusters in polysilicon. At low anneal temperatures, the B profiles in single crystal Siare shallower than the As profiles. This is because most of the B in polysilicon films is immobile during annealing near the peak region where the solid solubility limit is exceeded, and because of low B segregation at grain boundaries, thereby reducing the impactof grain boundaries in terms of high diffusivity. At high anneal temperatures, the native oxide at the interface breaks up and causes the polysilicon layer to align epitaxiallywith respect to the underlying substrate. Time to breakup of interfacial oxide depends on dopant species and anneal temperatures. Oxide breakup takes longer for As-doped samples than for B-doped samples. For high thermal budget anneals, B diffusion into the substrate is greater than As diffusion because of higher B diffusivities in single crystal Si.