We have measured the internal friction (Q-1) of amorphous silicon nitride (a-Si3Nx) films prepared by a variety of methods, including low-pressure chemical-vapor deposition (LPCVD), plasma-enhanced chemical-vapor deposition (PECVD), and hot-wire chemical-vapor deposition (HWCVD) from 0.5 K to room temperature. The measurements are made by depositing the films onto extremely high-Q silicon double paddle oscillator substrates with a resonant frequency of ~5500 Hz. We find the elastic properties of these a-Si3N4 films resemble those of amorphous silicon (a-Si), demonstrating considerable variation, depending on the film growth methods and post deposition annealing. The internal friction for most of the films shows a broad temperature-independent plateau below 30 K, characteristic of amorphous solids. The values of Q-1, however, vary from film to film in this plateau region by more than one order of magnitude. This is typical for tetrehedrally bonded amorphous thin films, like a-Si, a-Ge, and a-C. The PECVD films have the highest Q-1 just like an ordinary amorphous solid, while LPCVD films have an internal friction more than one order of magnitude lower. All the films show a reduction of Q-1 after annealing at 800°C, even for the LPCVD films which were prepared at 850°C. This can be viewed as a reduction of structural disorder.

Microcrystalline silicon (mc-Si:H) has recently been proven to be a promising material for thin-film transistors (TFTs). We present mc-Si:H TFTs fabricated by plasma-enhanced chemical vapor deposition at temperatures below 200°C in a condition similar to the fabrication of amorphous silicon TFTs. The mc-Si:H TFTs exhibit device mobilities exceeding 30 cm2/Vs and threshold voltages in the range of 2.5V. Such high mobilities are observed for long channel devices (50-200 mm). For short channel device (2 mm), the mobility reduces to 7 cm2/Vs. Furthermore the threshold voltage of the TFTs decreases with decreasing channel length. A simple model is developed, which explains the observed reduction of the device mobility and threshold voltage with decreasing channel length by the influence of drain and source contacts.

In our previous works we have studied the fabrication process and characterization of single cell micro-bolometers based on germanium thin films deposited by low frequency (LF) PECVD technique at low temperature and fully compatible with the IC fabrication technology. We have demonstrated promising properties of those devices for further development of IR imaging systems.

In this work we report the study of a fabrication process and characterization of one dimensional array of 32 un-cooled micro-bolometers. We have used surface micro-machining techniques for the array fabrication onto a silicon wafer. The micro-bolometers in the array have a “bridge type” configuration, in which a SiNx supporting film is suspended 2.5 μm from the substrate by two legs forming the bridge in order to provide sufficient thermo-isolation for thermo-sensing layer, which is deposited by LF PECVD over it. The a-GexSiy:H film used in this devices showed high activation energy Ea= 0.34 eV, providing high thermal coefficient of resistance, TCR=α=0.043 K-1 and improved but still high resistance. We studied the effect of include boron in the a-GexSiy:H film deposition process in order to reduce its undesirable high resistance and we used this layer (a-GexBySiz:H) as thermo-sensing film in the micro-bolometers arrays also. The active area of the cells in the array is Ab=70×66 μm2 and the area of the array including interconnection lines and pads is A=1600×3120 μm2. The temperature dependence of conductivity σ(T), current-voltage characteristics I(U) and spectral noise density have been measured in the micro-bolometers in the array in order to characterize and compare their performance characteristics, such as responsivity and detectivity.

A major route to improving solar cell efficiencies is by improving light trapping in solar absorber layers. Traditional light trapping schemes involve a textured metallic back reflector that also introduces losses at optical wavelengths. Here we develop alternative light trapping schemes with a-Si:H thin film solar cells, that do not use metallic components, thereby avoiding losses. We utilize low loss one-dimensional photonic crystals as distributed Bragg reflectors (DBR) at the backside of the solar cells. The DBR is constructed with alternating layers of crystalline Si and SiO2. Between the DBR and the absorber layer, there is a layer of 2D photonic crystal composed of amorphous silicon and SiO2. The 2D photonic crystal layer will diffract light at oblique angles, so that total internal reflection is formed inside the absorber layer. We have achieved enhanced light-trapping in both crystalline and amorphous silicon solar cells at near-infrared wavelengths where absorption lengths are very large. Very high absorption is achieved throughout optical wavelengths. The optical modeling is performed with a rigorous 3 dimensional scattering matrix approach where Maxwell¡¯s equations are solved in Fourier space.

Laser crystallization of silicon is discussed for forming polycrystalline silicon thin films used to fabricate polycrystalline silicon thin film transistors (poly-Si TFTs). Laser-induced rapid heating is important for crystalline film formation with a low thermal budget. Structural and electrical properties of poly-Si films are discussed. Reduction of electrical active defects located at grain boundaries is essential for achieving poly-Si TFTs with high performances. The internal film stress is attractive to increase the carrier mobility. Recent development in laser crystallization methods with pulsed and continuous wave (CW) lasers is then reviewed. Control of the heat flow results in crystalline grain growth in the lateral direction, which is essential for fabrication of large crystalline grains. We also report an annealing method using a high power infrared semiconductor laser. High power lasers will be attractive for rapid crystallization of silicon films over a large area and activation of doped regions.

This study investigates the used of aluminum-induced crystallization of amorphous silicon is a potential bonding mechanism for a sandwich stack of films between two silicon substrates. Similar procedures using copper diffusion bonds have been in use, but these require temperatures as high as 400°C. Using the crystallization of amorphous silicon as the bonding mechanism has allowed the bonding temperature to be lowered by more than 100 K. Fracture experiments for a low-k material were conducted, and the results using amorphous silicon bonding was compared to epoxy bonding control experiments. Essentially identical results were obtained for the two bonding mechanisms. Low-temperature bonding techniques are of great interest to future progress in the microelectronics industry, and these results are promising advances.

A series of silicon thin films was made by very high frequency plasma enhanced chemical vapour deposition (VHF PECVD) at substrate temperatures below 100 °C at different hydrogen to silane dilution ratios. The electronic properties of these layers were studied as a function of the surface crystalline fraction as determined accurately from a combination of microscope images at different length scales (gathered by using different types of microscopes). The results show that the electrical conductivity increases monotonously as a function of crystalline surface coverage and no discontinuity is observed at the percolation threshold. An increase in conductivity of four orders of magnitude for layers with a high crystalline content is observed after annealing at temperatures up to 170 °C. Combined with the information that oxygen is incorporated at Si-H surface bond sites, this suggests that doping of the intergrain boundaries by oxygen might be dominantly responsible for the electronic properties of mixed phase silicon.

The effect of power density and thickness on aluminum-induced crystallization (AIC) of amorphous silicon (a-Si) formed with plasma enhanced chemical vapor deposition (PECVD) was studied by using N2-protected conventional furnace reaction and optical microscopy. With the deposition power density ranging from 0.05 to 1.00 W/cm2 and the thickness from 500 to 5000Å, it was found that a low power density as well as a large a-Si thickness could result in a decrease of activation energy and therefore a significant reduction of the AIC reaction temperature. Scanning and transmission electron microscopy and X-ray diffraction were used to check the crystallinity and quality of the AIC thin films. High quality polysilicon thin films were achieved at an AIC reaction temperature as low as 120°C.

We study resistive losses at (p)c-Si/(p)Si:H/(n)ZnO heterojunction back contacts for high efficiency silicon solar cells. We find that a low tunnelling resistance for the (p)a-Si:H/(n)ZnO part of the junction requires deposition of Si:H with a high hydrogen dilution RH > 40 resulting in a highly doped μc-Si:H layer. Such a μc-Si:H layer if deposited directly on a Si wafer yields a surface recombination velocity of S  180 cm/s. Using the same layer as part of a (p)c-Si/(p)Si:H/(n)ZnO back contact in a solar cell results in an open circuit voltage Voc = 640 mV and a fill factor FF = 80 %. Insertion of an (i)a-Si-layer between the μc-Si:H and the wafer leads to a further decrease of S and, for the solar cells to an increase of VOC. However, if the thickness of this intrinsic layer exceeds a threshold of 3 nm, resistive losses lead to a degradation of the fill factor of the solar cells. These resistive losses result from a valence band offset δEV between a-Si:H and c-Si of about 600 meV. The fill factor losses overcompensate the VOC gain such that there is no benefit of the (i)a-Si:H interlayer for the overall solar cell performance when using an (i)a-Si:H/(p)uc-Si:H double layer.

The rapid crystallization of amorphous silicon utilizing the rf inductive coupling thermal plasma jet of argon is demonstrated. Highly crystallized a-Si films were fabricated on th-SiO2 and textured a-Si:H:B/SnO2/glass by adjusting the translational velocity of the substrate stage. The H concentration in the films decreased from 1021 cm-3 to 1019 cm-3 with no marked increases in oxygen and nitrogen impurity concentrations and defect density. The crystallization proceeds from the bottom to front surface in terms of the volume expansion during the solidification and crystallization of liquid Si.

Large area digital imaging made possible by amorphous silicon thin-film transistor (a-Si TFT) technology, coupled with a-Si photo-sensors, provides an excellent readout platform to form an integrated medical image capture system. Major development challenges evolve around

optimization of pixel architecture for detector fill factor, signal propagation performance, and manufacturability, while suppressing noise stemming from pixel array and external electronics. This work analyzes a novel vertically integrated pixel design based on signal readout and noise performance, and compares with conventional co-planar and continuous detector architectures. In addition, the analysis will consider various substrate options including glass and robust substrates such as polymer and metal foil. Our evaluation have demonstrated state-of-the-art radiographic detector system with electronic noise under 2000 electrons at 150 µs frame time for an imaging arrays on robust substrate.

The grain size of thermally crystallized a-Si films is controlled by the nucleation, rN, and growth, rG, rates according to the standard Avrami's theory. Despite this evidence, most papers devoted to improve the crystallized grain size analyze their results with a qualitative reference to this theory. In this paper, we will show that one can identify the standard set of rN and rG values for a-Si and that experiments show that deviations from this standard values always result in a smaller grain size. It is also shown that one cannot expect any substantial improvement with non-conventional heat treatments. Finally, it is argued that a larger grain size is expected from a-Si films containing, in their as-grown state, a controlled density of embedded nanocrystals.

To reduce the harmful influence of grain boundaries in polycrystalline Si layers we make absorber layers on foreign substrates with columnar grains with a grain width larger than the grain thickness. Such layers with a grain size in the range of ~1-100 µm can be obtained by aluminum-induced crystallization and epitaxy. Until now however, the open-circuit voltage of solar cells made from such layers was quasi-independent of the grain size. To understand this fact, defect etching and Electron Backscattered diffraction (EBSD) measurements were performed to investigate the crystallographic defects. A very large density (~ 109 cm-2) of intra-grain defects (IGD) was found. Room temperature Electron Beam Induced Current (EBIC) measurements were done to localize and investigate the electrically active defects. The intra-grain defects found with defect etching showed a strong recombination activity. These results indicate that the unexpected quasi-independence on the grain size of the open-circuit voltage of our pc-Si solar cells is due to the presence of numerous electrically active intra-grain defects.

Hydrogenated amorphous silicon (a-Si:H) n-i-p photodiodes may be used as the pixel sensor element in large-area array imagers for medical diagnostics applications. The dark current level is an important parameter that dictates the performances of these types of pixelated imaging devices. Through measurements performed at different ambient temperatures, the leakage current components of segmented a-Si:H n-i-p photodiodes were extracted and analyzed. It was found that the central component of the reverse current depends exponentially on bias and temperature. The activation energy of this component is independent of bias. The peripheral component of reverse current exhibits linear bias dependence at temperatures up to 50°C, while the contribution of this component diminishes at high temperatures. The dependence of dark current components on bias and temperature could be described by compact analytical equations. The model of forward and reverse dark current characteristics in temperature range was implemented in Verilog-A hardware description language.

Previously, we reported improved silicon epitaxy by hot-wire chemical vapor deposition (HWCVD) between about 600 and 650°C. Such temperatures are compatible with the thickening of large-grained Si seed layers on borosilicate glasses or other inexpensive substrates. Here, we provide detailed real-time spectroscopic ellipsometry (RTSE) and x-ray diffraction (XRD) analysis of two films grown near 600°C. A film grown at 594°C shows breakdown to a polycrystalline phase, while a film grown at 627°C is entirely epitaxial. Transmission electron microscopy (TEM) of this epitaxial film shows dislocation defects that originate at the substrate/film interface, suggesting that an optimized surface preparation could yield lower defect densities.

We present in this paper results about the analysis of photocurrent and spectral response in a-SiC:H/ a-Si:H pinpin and pinip structures. Our experiments and analysis reveal the photocurrent profile to have a strong nonlinear dependence on the externally applied bias and on the light absorption profile, i.e. on the incident light wavelength and intensity. Our interpretation points out the cause of such effect to a self biasing of the junctions under certain unbalanced light generation of carriers and to an asymmetric reaction of the internal electric fields to the externally imposed bias. The possibility to relate such a behavior to the light intensity and wavelength indicates realistic hypothesis of using these structures and this effect for color recognition sensors.

We present results about the experimental characterization of the structures and numerical simulations obtained with the program ASCA. Considerations about electrical field profiles and inversion layers will be taken into account to explain the optical and voltage bias dependence of the spectral response. Our results show that in both structures the application of an external electrical bias (forward or reverse) mainly influences the field distribution within the less photo excited sub-cell.

We report a low temperature high quality oxide growth of nano-structured silicon thin films on silicon substrates obtained through a hydrogenation-assisted PECVD technique followed by a plasma enhanced oxidation process. The deposited layers were investigated and compared with respect to their electrical, optical and stoichiometrical properties by means of Ellipsometry, Rutherford backscattering (RBS), Raman spectroscopy, Fourier transform infrared (FTIR) spectroscopy, and by current voltage and capacitance voltage measurements on metal-oxide-semiconductor (MOS) structures.

This paper reports the first successful attempt to fabricate amorphous silicon (a-Si:H) n-i-p photodiodes on a thin stainless-steel foil substrate for medical X-ray imaging applications. Two architectures of the n-i-p-photosensor, where the top electrode is based on amorphous or polycrystalline ITO, have been developed and characterized. The impact of critical fabrication steps including the deposition of semiconductor layers, dry etch of the NIP stack, diode passivation and encapsulation, as well as a contact formation on the device performance is presented and discussed. The test structures comprising segmented photodiodes with an active area ranged from 0.126 × 0.126 to 1 × 1 mm2 have been fabricated on stainless-steel foils and on glass substrates for the purposes of process characterization. The fabricated samples are evaluated in terms of current-voltage, capacitance-voltage, and spectral response characteristics.

High-temperature silicon dioxide chemical vapor deposition (HTOCVD), using SiH2Cl2 and N2O, can realize dense and conformal oxide film, not only on large size silicon wafers, but even inside of microscopic silicon trenches, at high-temperature around 800°C.

In this work, we investigated the kinetics of HTOCVD using a commercial scale low pressure (LP) CVD reactor, focusing on the correlation between deposition rate and surface-to-volume ratio (S/V ratio), which is a specific surface area of substrate wafer divided by the space volume between two adjacent wafers. We also investigated the deposition rate profile on wafers, and along the axial direction of the reactor near the region where one, two or three substrate wafers are extracted from the quartz holder. The deposition rate profiles on wafer characteristically change from skillet-like to pancake-like, according to the increase of wafer spacing. The influence on the deposition rate of wafer spacing spreads to ranges not only downstream, but also upstream in the gas flow. These experimental results strongly suggest that in the HTOCVD gas-phase reactions through intermediate states of active species contribute to deposition reaction as well as direct deposition reaction of source gases on Si surface.

The defect density in thin film silicon was increased using low temperature 2MeV electron irradiation up to a factor of 1000. More than 30 samples of different structure from highly crystalline to amorphous were prepared with PECVD and irradiated to study the dynamics of defect accumulation and role of the material structure in this process.