In this paper, we investigate the chemical vapor deposition (CVD) of Ge nanocrystals (NCs) directly on hafnium oxide HfO2 dielectric for non-volatile memory applications. Germane GeH4 was used as a precursor. Atomic force microscopy (AFM), X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), and scanning electron microscopy (SEM) were used to characterize the Ge NCs. The dependence of the Ge NC size and density on the deposition temperature, deposition time, and flow rate was explored. A high Ge NC density of 1011 cm-2 was obtained at a deposition temperature of 600°C, with a mean diameter of about 16 nm. MOS capacitors with CVD Ge NCs embedded in the HfO2 gate dielectric were fabricated. Hysteresis of capacitance-voltage (C-V) characteristics of capacitors with Ge NCs was observed, demonstrating memory effect.

Several small clusters of Ga and In with As and V atoms are pre-designed to study effects of spatial constraints on electronic and magnetic properties of such clusters by means of the Hartree-Fock (HF) method. The obtained electronic energy level structures (ELSs), optical transition energies (OTEs) and spin densities of these clusters are compared to those specific to the corresponding clusters nucleated without spatial constraints. The pre-designed indium-based clusters demonstrate the enhanced spin densities as compared to those of the gallium-based clusters with equal numbers of V atoms, and thus can be of interest for applications in spintronic and magneto-optic memory materials development.

One-transistor (1T) memory devices with MFIS (Metal, Ferroelectrics, Insulator, Silicon) and MFMIS (Metal, Ferroelectrics, Metal, Insulator, Silicon) structures have been widely studied. These memory devices exhibit memory working functions but very poor retention properties. Three possible mechanisms are responsible for the poor retention of 1 T ferroelectric memories: namely, charges trapping within the gate oxide and ferroelectric film, floating gate effect, and the depolarization field. In order to overcome these problems, a novel ferroelectric transistor design using a semiconductive oxide film in place of the gate dielectric has been fabricated. The device structures are Pt/PGO/InO2/Si (MFSoxS) and Pt/PGO/Ir/InO2/Si (MFMSoxS). There is no insulator in the gate stack. These device structures do not have floating gate and the depolarization field is very low. Therefore, the memory retention time can be very long. In this paper, we report the device structures, integration processes and the working properties with improved retention properties of the Pt/PGO/InO2/Si (MFSoxS) and Pt/PGO/Ir/InO2/Si (MFMSoxS) devices.

We have investigated the switching properties of ferroelectric lead strontium titanate (Pbx Sr1-x)TiO3 (PST) capacitors using epitaxial and polycrystalline La0.5Sr0.5CoO3 (LSCO) electrodes to evaluate its potential for non-volatile memory applications (FRAM'S). The electrical performance of the PST based capacitors grown on epitaxial and polycrystalline LSCO substrates were evaluated through Polarization-Voltage (P-V) and Fatigue measurements. The [001] preferentially oriented PST ferroelectric capacitor did not show a decrease in polarization up to 108 switching cycles at an applied voltage of 4 volts and a frequency of 100 kHz. Polycrystalline PST films, on the other hand were severely fatigued. It is proposed that the good performance of the PST capacitors can be attributed to the high degree of orientation of the PST films in the [001] direction induced by the epitaxial LSCO film. However, after 1010 switching cycles in the fatigue tests, the decay of the non-volatile polarization of these films was about 18% of its initial value. We use a simple model to describe two major microscopic scenarios for the suppression of polarization at the electrodes interfaces. This model is supported by Auger Electron Spectroscopy to determine the bulk and interfacial characteristics. The depth distribution of the elements of the PST film is nearly uniform throughout the volume of the film; however the relative concentrations of Pb and O were abnormally distributed on the surface. It is concluded that, in spite of the good performance due to the favorable conditions for the growth of the PST films provided by the textured LSCO, higher quality interfaces and better control of composition is necessary to improve on fatigue.

Silicon nanocrystals can be used in non-volatile memory devices to reduce susceptibility to charge loss via tunnel oxide defects, allowing scaling to smaller sizes than possible with conventional Flash memory technology. In order to optimize device performance, it is desirable to maximize the nanocrystal density and surface coverage, while maintaining sufficient inter-crystallite separation to limit electron tunneling between adjacent crystallites. Ideally, crystallite densities in excess of 1012cm-2 with relatively narrow particle size distributions must be obtained, posing a significant challenge for process development and control. In order to facilitate development of such a process, a rate-expression-based model has been developed for the nucleation and growth of silicon nanocrystals on SiO2 in a CVD process. The model addresses the phenomena of nucleation, growth, and coalescence and includes the effects of exclusion zones surrounding the growing nuclei. The model uses a phenomenological expression to describe the nucleation rate and assumes that following nucleation, crystallite growth is dominated by gas-phase deposition processes, analogous to CVD of polycrystalline silicon. The model-predicted time-evolutions of crystallite densities and crystallite size distributions are consistent with experimental distributions as measured by Scanning Electron Microscopy (SEM). By coupling the model to a reactor-scale model of polysilicon CVD, it is possible to predict variations in the crystallite size distributions at various locations across a wafer as a function of reactor settings (temperature, pressure, flow rates, etc…). This in turn can be used for process control and optimization in order to ensure uniform deposition of nanocrystals in a large-scale manufacturing environment.

A method of forming a sheet of Ge nanocrystals in a SiO2 layer based on molecular beam epitaxy (MBE) and rapid thermal processing (RTP) is presented. The method takes advantage of the very high precision by which a very thin Ge layer can be deposited by MBE. With proper choice of process parameters the nanocrystal size can be varied between ∼3 and ∼8 nm and the area-density between ∼1×1011 and ∼1×1012 dots/cm2. The tunneling oxide thickness is determined by the thickness of a thermally grown SiO2 layer, and is typically 4 nm. C-V measurements of MOS capacitors reveal hole and electron injection from the substrate into the nanocrystals. Memory windows of about 0.2 and 0.5 V for gate-voltage sweeps of 3 and 6 V, respectively, are achieved.

Electrical bistable states with the conductivity different by more than four orders in magnitude were observed in a polymer film sandwiched between two metal electrodes. This polymer film was composed of gold nanoparticles, 8-hydroxyquinoline and polystyrene, and was formed by a solution process. The film can be programmed between the two electrical states by an electric field. The as-prepared device, which was in a low conductivity state, exhibited an abrupt increase of current when the device was scanned up to 2.8 volt (V). The high conductivity state can be returned to the low conductivity state at a voltage of –1.8 V in the reverse direction. The device has a good stability in both the states. The transitions are nonvolatile, and the transition from the low to the high conductivity state takes place in nanoseconds, so that the device can be used as a low-cost, high-density, high-speed, and nonvolatile memory. The switching mechanism was studied by investigating the current-voltage characteristics, the temperature dependence of the current, the surface potential atomic force microscopy and the energy levels of the materials. The electronic transition is attributed to the electric-field induced charge transfer between the gold nanoparticles and 8-hydroxyquinoline molecules.

With respect to the operation of a Phase-change Random Access Memory (PRAM or PcRAM), we studied the effect of the contact between the electrode metal and the chalcogenide glass, N2 doped Ge2Sb2Te5 in this report. We investigated a change of the resistance-programming current pulse (R-I) curve varying the contact size and the electrode material. Also we tested the surface oxidation of the electrode. We found that the programming current, the resistance of the programmed state (“RESET”) and the erased state (“SET”) were highly dependent on the above parameters. These results are presented and a more effective way to the high density PRAM will be proposed.

We have studied a set of MOS cell structures with 30 nm thick thermal oxide implanted with Si at high doses (10, 15 and 20 atomic % at projected range) in which Si nanocrystals (Si-nc) have been precipitated by annealing at 1100 °C. Energy filtered transmission electron microscopy reveals: i) a central layer of Si-nc with a mean size of 2.8 nm; ii) a control oxide of 12.5 nm completely free of Si-nc and iii) a tunnel oxide of about 2.5 nm. This narrow tunnel oxide enables the direct tunnel for charging and discharging which is a must for high speed and good reliability. However, this results in typical retention times ranging from only few hours to several months, depending on the concentration of Si-nc. For developing low voltage memories we have focused on the highest Si excess sample, which shows fast write times (tens of μs) at very low gate fields (±2 MV/cm or ±6V). The onset of Fowler-Nordheim conduction is of about ±6 MV/cm by J-V measurements (±18V), which means that the structure works in a direct tunnel regime. To increase the retention time we have performed an additional annealing step in diluted O2 for 16 and 32 minutes, resulting in a dramatic increase in the retention times, which is attributed to the re-growth of an additional tunnel oxide which eliminates surface roughness, remaining Si excess and defects at the Si-SiO2 interface. This additional oxidation step produces also a decrease in the mean size of the Si-nc distribution. Thus, we increase the retention time beyond the 10 years standard limit. Finally, the writing times can be traded-off by increasing slightly the program voltage up to ±2.7 MV/cm or ±8V.

The quest for a nonvolatile memory FET based on the metal-ferroelectric-(insulator)-semiconductor (MF(I)S) gate stack concept has greatly intensified in recent years. In principle, such a memory device (MF(I)S) could be a building block of an ideal memory technology which offers random access, high speed, low power, high density and non-volatility. In practice, however, none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days so far. These results are a far cry from the 10-year retention time requirement for non-volatile memory devices. This paper reveals progress and optimization that grain size, interfacial properties, and crystallinity of the annealed ferroelectric SrBi2Ta2O9 (SBT) films have a strong impact on the size of the memory window, as does the choice of the buffer layer material. The properties of SiN buffer layer sandwiched between SBT and Si are discussed. Switches in the polarization of the ferroelectric SBT play a key role for both the ferroelectric-polarization-dominated and the trapping-dominated memory windows. Preliminary results on MFIS capacitors and transistors are reviewed, limited retention time has been observed. A closer look at the physics of device operation reveals two major causes of the short retention time: (1) depolarization fields; (2) finite gate leakage current and the associated charge trapping. Here, the origins of these problems are analyzed and practical difficulties in attempting to realize nonvolatile ferroelectric 1-T memory devices are illustrated. Two possible solutions have been proposed to circumvent problems associated with the finite retention time in ferroelectric FETtype memories: (1) memory refreshes as done in the FEDRAM cell, (2) single-crystallize the ferroelectric film.

A hydrothermal method is a unique method to deposit ferroelectric thin films utilizing chemical reaction in solutions. In addition to the low reaction temperature below 200°C, its simple process procedure, automatically aligned polarization and a three-dimensional deposition are advantages. In this study, a lead titanate epitaxial thin film was obtained on a strontium ruthenate bottom electrode sputterd on strontium titanate (100). The highresolution X-ray diffraction mapping showed the film was perfectly c-axis oriented. The transmission electron microscope observation revealed that the film had no lattice dislocation at the interface between lead titanate and strontium ruthenate. A remanent polarization of 96.5μC/cm2 was measured with the single crystal-like DE hysteresis curve. The observation of a scanning nonlinear dielectric microscopy indicated that this film did not contain any defect such as an a-domain and a grain boundary even on the nano scale. With various pulse parameters, nano-domain dots were patterned and the minimum dot radius of inverted domain was 12 nm corresponding to data storage density of 1Tbit/inch2.

In this work, we demonstrate a MISFET memory device that incorporates a monolayer of Langmuir-Blodgett (LB) deposited gold nanoparticles as floating gate charge storage elements. The FET device is fabricated on a SOI substrate using conventional silicon processing. The nanoparticle layer is separated from the channel area of the FET with a 5 nm thermal SiO2 layer and is isolated from Al gate contact with a LB-deposited organic insulator layer. The memory effect is tested using voltage pulses on the gate of the device and monitored through drain current measurements. The nanocrystals can be charged either from the channel through the thermal oxide layer by applying pulses smaller than 5 V or from the gate through the organic insulator for higher voltage depending on the pulse duration.

To eliminate the interface reaction problems between ferroelectric and semiconductor in MFS (metal-ferroelectric-semiconductor) as well as ferroelectric and insulator in MFIS (metal-ferroelectric-insulator-semiconductor) structures, a gate layer sandwich of the MFMIS (metal-ferroelectric-metal-insulator-semiconductor) is proposed. This structure consists of Pt-SBT-Pt-ZrO2-SiO2-Si stacks. In the MFMIS structure the MIS capacitor is separated from the ferroelectric MFM capacitor through a metal as a floating gate. Therefore, the MIS capacitor with SiO2 and ZrO2 as an insulator with excellent interface properties can be used and MFM acts as an ideal ferroelectric capacitor. As MFMIS is a series combination of MFM and MIS capacitors, it behaves as a voltage divider. The gate voltage is divided according to the capacitance ratio of the MIS and MFM structures. Since the fabricated devices have access to the floating gate, characteristics of the MFM and MIS capacitors can be determined independently to compare the characteristics of the MFMIS structure as a single capacitor. The ferroelectric can be programmed in one direction and the field effect due to that can be analyzed. The MFMIS structures showed significant memory window due to the polarization of ferroelectric thin films but the retention time was short. The short retention time was due to the depolarization field being larger than coercive field of the ferroelectric thin film.

Pb(Zr, Ti)O3 (PZT) films were deposited into sub-micron trench structure consisting of SiO2/TiAlN/Ti/SiO2/Si to investigate their thickness and composition conformality by pulsed-metalorganic chemical vapor deposition (MOCVD) using liquid delivery source-supply system. Bis(dipivaloylmethanato)lead [Pb(DPM)2], tetrakis(1-methoxy-2-methyl-2-propoxy)zirconium [Zr(MMP)4] and tetrakis(1-methoxy-2-methyl-2-propoxy)titanium [Ti(MMP)4] were used as Pb, Zr and Ti source materials, respectively. In Arrhenius plot, the slopes of the straight lines for the constituents Pb, Zr and Ti in PZT film were almost the same at a lower deposition temperature (Td) region as well as a higher Td one. This means the composition change in the film against the Td can be suppressed by using Pb(DPM)2-Zr(MMP)4-Ti(MMP)4-O2 source system. From the results of Arrhenius plot, the Tds were fixed on 450 and 540°C as lower and higher temperatures, respectively. At both Tds, the sidewall-bottom step coverage (SCs-b) was approximately 70 %, while the sidewall step coverage (SCsw) reached excellent values above 90 %. It is suggested that low SCs-b value was caused by crystallization of the PZT films at the bottom of the trench because underlayer of the film at this area was not SiO2 but crystalline TiAlN. On the other hand, no significant composition fluctuation was observed along the depth direction of the sidewall. These results mean that the film deposited at 540°C had almost the same level in terms of thickness and composition conformality as that deposited at 450°C.

In silicon nanocrystal (nc) based metal-oxide-semiconductor (MOS) memory structures a fine control of the Si nc location in the gate oxide is required for the pinpointing of optimal device architectures. In this work, we show how to manipulate and control the depth-position, size and surface density of two dimensional (2D) arrays of Si ncs embedded in thin (<10 nm) SiO2 layers, fabricated by ultra-low-energy (typically 1 keV) ion implantation and subsequent annealing. Particular emphasis is placed upon the influence of implantation, annealing conditions and oxide thickness on the nanocrystal characteristics (e.g. size, density) and the charge storage properties of associated MOS structures. Structural investigation is performed by using specific characterization methods including Fresnel imaging for the measurement of the injection distance between the substrate and the nc band, as well as spatially resolved Electron Energy Loss Spectroscopy using the spectrum-imaging mode of a Scanning Transmission Electron Microscope to evaluate the size distribution and density of the ncs.

GeH4 is thermally cracked over a hot filament depositing 0.7–15 ML Ge onto 2–7 nm SiO2/Si(100) at substrate temperatures of 300–970 K. Ge, GeHx, GeO, and GeO2 desorption is monitored through temperature programmed desorption in the temperature range 300–1000 K. Ge bonding changes are analyzed during annealing from 300–1000 K with X-ray photoelectron spectroscopy (XPS). Low temperature desorption features are attributed to GeO and GeH4. No GeO2 desorption is observed, but GeO2 decomposition to Ge through high temperature pathways is seen above 700 K. Germanium oxidization results from Ge etching of the oxide substrate, which is demonstrated through XPS. Ge nanoparticle formation on SiO2 is demonstrated using the agglomeration process. With these results, explanations for the difficulties of conventional chemical vapor deposition to produce Ge nanocrystals on SiO2 surfaces are proposed.

Fatigue is an important problem to be considered if a ferroelectric film is used for non-volatile memory devices. In this phenomena, the remanent polarization and coercive field properties degrades in cycles which increase in hysteresis loops. The reasons have been attributed to different mechanisms such as a large voltage applied on ferroelectric film in every reading process in Ferroelectric Random Access Memory (FeRAM) or memories for digital storage in computer, grain size effects and others. The aim of this work is to investigate the influence of the crystallization kinetics on dielectric and ferroelectric properties of the Pb(Zr0.53Ti0.47)O3 thin films prepared by an alternative chemical method. Films were crystallized in air on Pt/Ti/SiO2/Si substrates at 700°C for 1 hour, in conventional thermal annealing (CTA), and at 700°C for 1 min and 700°C 5 min, using a rapid thermal annealing (RTA) process. Final films were crack free and presented an average of 750 nm in thickness. Dielectric properties were studied in the frequency range of 100 Hz – 1 MHz. All films showed a dielectric dispersion at low frequency. Ferroelectric properties were measured from hysteresis loops at 10 kHz. The obtained remanent polarization (Pr) and coercive field (Ec) were 3.7 μC/cm2 and 71.9 kV/cm respectively for film crystallized by CTA while in films crystallized by RTA these parameters were essentially the same. In the fatigue process, the Pr value decreased to 14% from the initial value after 1.3 × 109 switching cycles, for film by CTA, while for film crystallized by RTA for 5 min, Pr decreased to 47% from initial value after 1.7 × 109 switching cycles.

MOS memory devices containing semiconductor nanocrystals have drawn considerable attention recently, due to their advantages when compared to the conventional memories. Only little work has been done on memory devices containing metal nanoparticles.

We describe the fabrication of a novel MOS device with embedded Pt nanoparticles in the HfO2 / SiO2 interface of a MOS device. Using as control oxide, a high-k dielectric, our device has a great degree of scalability. The fabricated nanoparticles are very small (about 5 nm) and have high density. High frequency C-V measurements demonstrate that this device operates as a memory device.

Poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric thin films are a potentially promising material for sensors or non-volatile memories. Imprint, the time-dependent resistance to polarization reversal, is a key material property that limits applications and is poorly understood. Based on experimental time and temperature dependences, we propose and investigate the link between imprint and charge trap states. A novel fast-ramp thermally stimulated current (TSC) measurement was developed to quantify and characterize the traps in an appropriate time-frame.

Thin films of P(VDF-TrFE) on oxidized Si substrates were characterized following controlled initialization, fatigue, polarization, and imprint. Trap states were thermally filled/emptied by temperature cycling between 20–100 °C, using heating and cooling rates between 1 and 5 °C/s. Dynamics of this fast-ramp TSC indicate the presence of not only trap states, but also reversible and non-reversible charge accumulation. The presence of electrically active traps were verified by measurements over 1–10 s imprint times. Trapped charge directly correlated with the log of the imprint time, with a rate of ∼0.12 /μC/cm2/decade.

Heteroepitaxial CeO2(80nm)/L0.67Ca0.33MnO3(400nm) film structures have been pulsed laser deposited on LaAlO3(001) single crystals to fabricate two terminal resistance switching devices. Ag/CeO2/L0.67Ca0.33MnO3 junctions exhibit reproducible switching between a high resistance state (HRS) with insulating properties and a semiconducting or metallic low resistance state (LRS) with resistance ratios up to 105. Reversible electrical switching is a polar effect achievable both in continuous sweeping mode and in the pulse regime.