In-situ resistivity measurements togheter with Auger electron spectroscopy, MeV 4He+ backscattering spectrometry, scanning electron microscope and x-ray diffraction have been used to investigate interactions between Al films and CVD polycristalline silicon layers deposited on thermally grown SiO2 on silicon. A sharp and well defined increase in resistivity around 450 °C has been associated to the erosion of the polysilicon and growth of Si crystallites in the metal film. The kinetic of the transformation has been studied by isothermal treatment over the 390–450 °C temperature range. An activation energy of 2.2 ± 0.2 eV has been measured. Similar results have been obtained by using treatments at constant heating rate. A critical analysis of the available data suggests that the rate limiting step is the nucleation of Si grains in the aluminum film. The driving force for the process can be identified to be the free energy difference between the initial and final states.

Formation of PtSi on As-doped polycrystalline Si is studied using different annealing sequences. An incomplete reaction between the Pt and Si is observed using a one-temperature anneal at 550 ° C, with unreacted Pt remaining in the film which is undesirable for the device processing. Using a three-temperature annealing sequence at 200–300–550 ° C in a N2-H2 mixture, a complete reaction is observed between Pt and Si, with no unreacted Pt detected. The results are similar to that using single crystal Si, except for the less-oriented PtSi formed. The three-temperature annealing process described has thus been shown useful to the fabrication of PtSi contacts at device areas containing either single crystalline or polycrystalline Si.

PtSi on As-doped polysilicon oxidizes rapidly at temperatures as low as 500 °C. The resulting SiO2-PtSi and PtSi-polysilicon interfaces are very rough. Silicide inclusions are present in the oxide, probably due to differences in oxidation rate between different PtSi grains. The presence of some inclusions near the SiO2 surface suggests that PtSi dissociates during oxidation. Rapid oxidation does not occur for PtSi on B or P-doped polysilicon, or for As concentrations of 1×1020 cm−3 or less.

The redistribution of boron implanted into TaSi2/poly-Si gates after high temperature anneals has been studied as a function of the implantation dose and energy as well as implantation scheme, i.e. boron implantation either into the silicide or into the poly-Si prior to TaSi2 deposition. SIMS measurements indicate that boron can easily diffuse from TaSi2 into poly-Si and vice versa at 900 °C. Independent of the implantation scheme, the boron concentration within poly-Si was found to saturate at approximately 1 × 1019 at/cm3 for boron doses greater than 5 × 1014 at/cm2. The excess of boron always accumulates within the silicide. The observed boron redistribution behavior within polycrystalline TaSi2/poly-Si layers is discussed in terms of combined lattice and grain boundary diffusion as well as grain boundary segregation.

We have grown Sb-doped poly-Si by thin-film reactions between Sb and amorphous Si (a-Si). The reactions and microstructures of the films were investigated by transmission electron microscopy (TEM) during in situ annealing and Auger electron spectroscopy (AES). The reactions either resulted in an amorphous Sb-Si (a-Sb-Si) alloy or caused crystallization of a-Si at low temperatures, depending on the film thickness of the a-Si layer as well as the heating rate. The electrical properties of the as-deposited and the annealed thin multi-layers deposited on SiO2 layer were determined using Hall measurements. After annealing at 1375 K for 60 minutes, Sb-doped poly-Si with a resistivity of 1.4×10−2 ohm-cm was obtained. A p-n junction was formed in a p-type Si substrate by using an a-Si/Sb/a-Si multi-layer as a diffusion source. The doping concentration in the Si substrate was obtained using secondary ion mass spectrometry (SIMS).

The passivation of grain boundaries and the neutralization of impurities in polycrystalline silicon, important processes for the improvement of performance of devices fabricated from this material, are discussed. The incorporation of hydrogen into grain boundaries is investigated using surface analysis methods. Volume-mapping techniques are used to identify the bonding mechanisms of the hydrogen in oxygen-free and oxygen-rich intergrain regions. Interactions between shallow acceptors (B, Al, Ga and In) and hydrogen in polycrystalline Si are studied. The bonding mechanisms involved in the acceptor neutralization process at the grain boundaries are evaluated using microanalytical techniques. Differences in the incorporation of molecular and atomic hydrogen, and corresponding variation in electrical passivation of grain boundaries, are observed. Volume-indexed AES and Auger difference spectroscopy data are complemented by scanning tunneling microscope images to confirm the direct hydrogen-silicon bonding in boron-doped grain boundaries.

This paper reviews the applications of polysilicon in microsensor technology and in the emerging field of microfabricated actuators. Polysilicon is an attractive material for thin-film strain gauges, and is also used to fabricate micromechanical structures. The need for better understanding of the non-electrical properties of polysilicon, such as Young's modulus, residual strain, ultimate strength, friction, and wear, is emphasized.

The influence of the density Ndis and recombination activity Sd of dislocations on the photocurrent Jsc, the spectral variation of Jsc and electron diffusion length Ln are computed by means of the Green's function. Sd is the surface recombination velocity of the space charge cylinder surrounding a dislocation line, assumed to be perpendicular to the illuminated surface of the cells.

It is found that the value and the spectral variation in the near infrared of Jsc and that of Ln, are dependent on Ndis and Sd, specially when Ndis and Sd are higher than 104 cm−2 and 104 cm s−1 respectively. A reasonnable agreement is obtained with experimental results.

The piezoresistive properties of boron-doped PECVD microcrystalline Si films (μc-Si) deposited on SiO2 coated Si, covar or quartz substrates have been investigated. The relations between the gauge factor (G.F.) and doping concentrations as well as the film thickness etc. have been obtained experimentally. The maximum longitudinal G.F. of 25 and 20 are measured for Si and covar substrates respectively. An expression for calculating G.F. of P-type μc-Si is derived theoretically by use of the splitting model of heavy and light hole band at k=0 and the thermionic emission theory. The calculated dependences of G.F. on the doping concentrations, grain size and trap state density agree well with the experimental results, which offer a better understanding of the piezoresistive characteristics of μc-Si or poly-Si, and enable optimized design and fabrication of μc-Si or poly-Si strain gauges.

Polycrystalline silicon is frequently deposited on single crystal silicon as a part of devices. The poly is used as both a dopant source and a low resistance contact in a modern method of fabricating high gain bipolar transistors. The randomness of polysilicon and its interface with the single crystal is an inherent source of differences among nominally identical transistors, however, and is a marked departure from the trend towards more and more perfect crystals that characterizes the rest of silicon technology.

The structural properties of the polysilicon-to-silicon interface affect the electrical characteristics of devices with polysilicon contacts. The current characteristics of advanced bipolar transistors with polysilicon base and emitter contacts are very sensitive to the presence of interfacial oxides and segregated dopants. Hence, bipolar transistors provide an excellent tool for studying the effects of different interfaces on minority carrier transport. The transport of majority carriers through polysilicon-to-silicon interfaces is best investigated with contact resistance structures. In this paper, we review the correlation between interface morphology and the electrical properties of a variety of interfacial layers, ranging from native oxides to chemical oxides or thermal nitrides. Measurements on both npn transistors and contact resistance structures provide quantitative information on the trade-off between base current (i.e. current gain) and emitter resistance. Within this constraint, a variety of electrical characteristics can be obtained by tayloring the nature of the polysilicon-to-silicon interface to the device application of interest.

A model for dopant pile-up in conjunction with a self-aligned polysilicon-emitter process model is presented that accurately predicts the total dopant profiles of the polysilicon layer, the interfacial pile-up and the underlying emitter, taken from SIMS measurements. The pile-up model assumes that, after the dopant is implanted into the polysilicon layer and instantaneously redistributes there during the anneal, the dopant diffuses from its polysilicon source into the interfacial and underlying base region. In the disordered interfacial region, the dopant transport occurs by hopping, with a, certain fraction of dopant sticking in vacant sites. The model for dopant pile-up is implemented into SUPREM III. As further support, device simulations, using the respective electrically active dopant profiles, are found to be in good agreement with measurements on self-aligned phosphorus-implanted transistors.

Electrical conduction data from heavily n and p-doped polysilicon thin films are presented. The sheet resistance in the range from 1 kΩ/□ to 100 Ω/□ is characterized over temperatures from 20°K to 450°K. It is shown that the polysilicon resistivity, larger than the corresponding crystalline value by a factor∼ 10 in the same doping range, is temperature insensitive. This larger resistivity is correlated to the degree of dopant activation and the mobility. The measured mobility varying from 8 to 20 cm 2/V.s is smaller than the corresponding crystalline value by a factor 10 ∼ 3.

Supersaturated high-conductivity polycrystalline silicon (polysilicon) formed by rapid thermal processing (RTP) is a promising new material for emitters, contacts and diffusion sources in advanced high-speed bipolar and MOS IC technologies.

A matrix of processing conditions was used to evaluate the effect of polysilicon thickness, implant dose, RTP conditions and the nature of the substrate on the dopant diffusion in both the polysilicon and single crystal substrate and also on the interface properties.

Results of conductivity measurements, spreading resistance profiling (SRP), secondary ion mass spectroscopy (SIMS), transmission electron microscopy (TEM) and Rutherford backscattering spectroscopy (RBS)/channeling are presented. The results have proved the formation of shallow, defect-free junctions and epitaxial emitters with low series resistance and improved contact properties.

The breaking up of a native oxide layer of a LPCVD amorphous Si/single crystal n+Si substrate interface by a rapid-thermal annealing was studied from the point of view of oxygen movement and morphological change. Oxygen atoms began to move at 1025 °C. After annealing at 1115 °C for 30sec, the quantity of oxygen atoms near the interface decreased dramatically and a silicon implant near the interface could enhance the decrease. More detailed observation was carried out by cross-section high-resolution transmission electron microscopy. After annealing at 940 °C for 30sec, the native oxide layer was continuous. On the qther hand, with a silicon implant near the interface, it changed into small oxide balls and an epitaxial growth occurred in the LPCVD layer with twins caused by these oxide balls. After annealing at 1115°C for 30sec, even without the silicon implant, a complete epitaxial growth occurred but it seemed that some SiOx particles dissolved into a single crystal Si layer near the interface.

Nonuniformities in the polysilicon-to-silicon interface and in the polysilicon structure are expected to produce a nonuniform diffusion front when arsenic is diffused from polysilicon during epitaxial alignment. Using transmission electron microscopy, we find surprisingly uniform arsenic diffusion fronts in the underlying silicon substrate following high temperature annealing. Several explanations of this result are proposed. We also report new evidence of a strong reduction in the time to achieve complete epitaxial transformation of the polysilicon when the polysilicon thickness is reduced. A corresponding reduction in the associated arsenic penetration depth is demonstrated.

The feasibility and advantages of using rapid thermal annealing to achieve a proper n+ polysilicon work function are demonstrated. Our data shows that RTA can be used to activate arsenic in the polysilicon gate after a regular furnace anneal or to diffuse and activate arsenic without any prior furnace anneal. Interface states and fixed charges due to RTA can be annealed out at 500°C for 30 min in forming gas. New insights into the diffusion, segregation, and activation of As in polysilicon during furnace and/or rapid thermal annealing have been obtained.

Advanced super thin(of less than 800Å) polysilicon films with the grain size of more than lum were developed by applying the Si+implanted amorphization and subsequent annealing. With this film, TFT with superior characteristics could have been fabricated on quartz or SiO2/c-Si substrate. At the process of 600°C, field effect electron mobility as large as 60cm 2/V.s. was obtained. Furthermore, using the high temperature process of 1000°C, electron and hole mobility increased to the value of 120 and 80cm2/V.s, respectively. The values of field effect electron mobility were almost constant over a wide temperature range. The CMOS scanner was fabricated and operated faster than 5MHz. These advanced polysilicon TFT's have a great impact on large size LSI.

Silicon implantation has been found to dramatically enhance the grain size of polysilicon crystallized from LPCVD a-Si by retarding the nucleation process at the substrate interface. Corresponding improvement in TFT device performance was also observed, resulting in field effect mobilities as high as 109 cm2/Vs in devices with 1000 Å thick Si active layer. This effect is more significant in device fabrication processes with higher temperature, possibly due to increasingly efficient removal of implant related defects.

The n- and p-channel field effect transistors are fabricated in as-deposited and grain boundary passivated polysilicon thin films. The performance of these thin film transistors (TFT's) is characterized and compared. Specifically, the transconductance and leakage behavior are discussed in detail in correlation with the grain boundary properties. The I-V characteristics are modeled from a unified point of view.