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Effects of Silicon Implantation and Processing Temperature on Performance of Polycrystalline Silicon Thin-Film Transistors Fabricated from Low Pressure Chemical Vapor Deposited Amorphous Silicon

Published online by Cambridge University Press:  22 February 2011

Anne Chiang ,
Tiao Y. Huang ,
I-Wei Wu ,
Mark H. Zarzycki  and
Mario Fuse
Anne Chiang
Affiliation:
Xerox Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304
Tiao Y. Huang
Affiliation:
Xerox Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304
I-Wei Wu
Affiliation:
Xerox Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304
Mark H. Zarzycki
Affiliation:
Xerox Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304
Mario Fuse
Affiliation:
Fuji Xerox Co., Ltd., 2274 Hongo Ebina-Shi Kanagawa-Ken, 243–04 Japan
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Abstract

Silicon implantation has been found to dramatically enhance the grain size of polysilicon crystallized from LPCVD a-Si by retarding the nucleation process at the substrate interface. Corresponding improvement in TFT device performance was also observed, resulting in field effect mobilities as high as 109 cm2/Vs in devices with 1000 Å thick Si active layer. This effect is more significant in device fabrication processes with higher temperature, possibly due to increasingly efficient removal of implant related defects.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 106: Symposium G – Polysilicon Films and Interfaces , 1987 , 305
Copyright
Copyright © Materials Research Society 1988

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References

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