The material properties of a-SiC:H alloys deposited by VHFGD are studied, with a special emphasis on the effect of hydrogen dilution of the plasma on layer quality. By incorporating these layers into p-i-n solar cells the authors compare layer properties and cell performance. Special attention is paid to the stability of the solar cells against light soaking. Furthermore, the authors show that the insertion of a buffer layer can, also in the case of entirely a-SiC:H cells, lead to a substantial increase of Voc. A reasonable stability of these cells is maintained by an appropriate doping of the buffer layers.

The electrical bandgap of microcrystalline silicon (μc-Si:H) p type layers used in a-Si:H alloy solar cells and the band edge discontinuities between μc-Si:H and a-Si:H alloys have been determined by internal photoemission measurements. The bandgap of μc-Si:H is found to be in the range of 1.50 to 1.57 eV, and the discontinuities at the conduction and the valence band edges are 0 to 0.07 and 0.26 to 0.35 eV, respectively. Use of these parameters in the numerical simulation of single-junction a-Si:H and a-SiGe:H alloy solar cells is found to predict experimental results of solar cell performance.

We have degraded a-Si:H p-i-n solar cells at Voc using both red and blue light to investigate the effect of a possible different spatial distribution of defects in the intrinsic layer. We have found that the I-V and the spectral response curves of the degraded cells depend on the total density of defects only and are not sensitive to the wavelength of the degradation light. These experimental results and some peculiar features of the spectral response of the degraded cells are explained with the aid of a numerical simulation program.

The i-layers of the middle and bottom cells in stable triple-junction amorphous silicon solar cells are composed of a-SiGe:H alloys which are graded in composition to enhance performance. We compare modeling and experimental results for three i-layer band gap grading schemes to determine the optimal profile. We find a good correlation between model trends and measured device parameters for all grading schemes. This is encouraging for the use of the model in predictive device design. We find that the highest white and red light performance do not necessarily have the same cell parameter set. Modeling and experiment indicate that thin cells without band gap profile and with suitably designed p/i and n/i buffer layers, have the best red light performance.

We report on modeling the evolution of the spatial defect profile in the i-layer of a-Si:H solar cells combined with tests of the model against the efficiency decay of amorphous silicon (a-Si:H) p-i-n solar cells under various light-soaking conditions. We use a finite-element device simulator. The defect density during light-soaking is calculated as a function of time and of position. The defect density evolves due to the combined effects of light-induced generation, assumed proportional to the product of free carrier densities, and of light-induced annealing, assumed proportional to the sum of carrier densities. We find that in thick cells defects close to the p-i interface affect cell efficiency less than bulk defects, and that in thin cells the defect density increases significantly in the central portion of the i-layer. However, in thin cells the high electric field masks the effect of the defect density increase.

A new technique to diagnose fill factor losses occurring in single-junction amorphous silicon (a-Si) alloy based nip solar cells has been explored. The method consists of the measurements of the fill factor of the device under blue and red light illumination and the current-collection loss obtained from the ratio of the quantum efficiency versus wavelength spectra at zero and reverse bias. Normally, the losses are higher at low and high wavelengths. It has been observed that there is a strong correlation between the values of the blue and red fill factors and the current collection losses at the pli interfaces and the bulk of the i-layer, respectively. The losses have been attributed to back diffusion of carriers at the pli interface and to the bulk of the i-Layer. There is a sensitive dependence between these losses and the texture of the substrate: textured substrates lead to higher losses compared to specular substrates. The technique has been used successfully to enhance the values of the red, blue, and AM 1.5 fill factors of both a-Si and amorphous silicon-germanium (a-SiGe) alloy single-junction cells on back reflectors by the optimization of device fabrication parameters. The optimized cells on textured back reflectors exhibit reduced losses. The paper presents an analysis of the experimental results.

Low resistivity (5×10−4Ω cm) and high transmittance (T > 82 %) ZnO films have been obtained by RF magnetron sputtering deposition of ZnO/Al2O3 (2.5 % wt.) target. The doped oxide films have been investigated by optical and electrical measurements and by scanning electron microscopy. The optimized recipes have been applied to the realisation of amorphous p-i-n solar cells back reflector in the structure: TCO/pin/ZnO/Ag.

The application of ZnO/Ag leads to an increase of the Jsc current of about 13% but a poorer fill factor steadily affects the characteristics of the devices. We demonstrate that a thicker n+ layer of about three times the standard one is effective in driving the FF toward the normal values.

The cells' behaviour has been ascribed to a thinning of the n+ layer resulting from a sputtering action of energetic oxygen atoms during the ZnO deposition process. This effect has been evidenced by measuring the absorbance of SnO2/a-Si (20 nm) /ZnO in comparison with SnO2/a-Si (20 nm) structure.

Hydrogenated amorphous silicon (a-Si:H) TCO/n+/i/Ni Schottky barrier solar cells were degraded with illuminations of white and red light through both sides of the structure. Because the forward dark I-V's are sensitive to the distribution and any spatial variation of defects in the i-layer, these measurements were used to characterize the degraded cell structures. These characteristics were analyzed using a charged defect distribution of gap states consisting of D+, D°, and D states derived from corresponding film analysis. It was found that the non-uniformities of light induced defects created in the i-layer can be represented by two regions of different defect densities. The relative densities depend on the direction of illumination and their ratio even with white light is about a factor of four. This non-uniformity is expected to be less for p-i-n cells which have higher built-in potential and hence electric fields.

In this article a new procedure to obtain alpha-hexathienylene (α-6T) thin-film-transistors (TFTs) with on/off ratios in excess of one million is reported. This procedure involves subjecting the TFTs to rapid thermal annealing. Previously, high on/off ratios have been achieved with improved device design and better chemical synthesis of α-6T oligomers. High on/off ratios, along with a switching time of ∼ 10 μs, render α-6T TFTs potential candidates as switching devices in active matrix displays. The experimental current-voltage (I-V) characteristics of oc-6T TFTs with channel length L = 4μm are also presented and a measured field effect mobility of 0.02 cm2/V-s is extracted from these characteristics using an analytical model which we have developed for short-channel α-6T TFTs.

Thin film transistors TFTs with the layered a-Si:H structure are presented and discussed. Compared with the conventional single layer a-Si:H TFT, transistor characteristics of this new structure can be superior or inferior, depending on the deposition condition and number of the bulk (non-interface) a-Si:H layers. The mechanism influencing transistor characteristics is discussed. Changes of these TFTs' characteristics are not significant, e.g., the mobility varies within 20%. More data are being collected to verify the statistical significance of this kind of TFT.

We present experimental results on the transient response of the source-drain current of laser crystallised polycrystalline silicon (poly-Si) thin film transistors (TFTs) over many orders of magnitude in time after the application of a voltage pulse to the gate electrode. This work follows on from similar measurements performed on amorphous silicon (a-Si) TFTs. Results showed a definite change in transient behaviour dependent on the magnitude of the gate bias. At a gate voltage of 5V there was an initial decay then a marked increase in the source-drain current beyond 1000 seconds. This variation of transient behaviour with gate bias was not seen in the a-Si case. For poly-Si the transient behaviour could not be split into different regimes in time (beyond the carrier transit time) whereas for a-Si TFTs the source-drain current showed a logarithmic decay at room temperature up to 100 seconds followed by a power law decay beyond 100 seconds. Our results indicate perhaps that only one mechanism exists for the observed transient decay of current, unlike the a-Si case. Measurements carried out at elevated temperature showed the current decay was independent of temperature indicating that the transient decay may be caused by charge injection via a tunnelling process into interface states, gate dielectric or passivation dielectric. Finally by carrying out measurements on TFTs after moderate positive voltage stressing and on TFTs with specially fabricated gate and passivation dielectrics it has been established that the transient decay is dielectric related and not a defect generation process.

Photo-transistor based a-Si:H image sensors allow the integration of photo-elements and pixel circuitry using standard TFT fabrication processes. While pixel circuitry use thin a-Si:H films (≈ 0.05μm) to minimize the contact resistance, photo-transistors require thick a-Si:H films (≈0.5μm) to maximize photo-sensitivity. We fabricated a new, high sensitivity photo-transistor structure using 0.05μ a-Si:H films. High optical sensitivity is achieved by separating the conduction paths of photo-generated electrons and holes using a secondary gate. Further, the optical path within the photo-transistor is doubled through manipulation of device layout. The photo-transistor show an Ilight/Idarkratio in excess of 103.

We compared the transient behavior of conventional and high-sensitivity photo-transistors. We found that both devices display an increase in current with time when biased in either the dark or illuminated conditions. The current increases by six orders of magnitudes then saturates within 200 seconds of bias application. Experiments indicate that this transient behavior is due to a rise in the conductivity of the gap region with time; measurements on 0.05μm thick photo-resistor structures showed that their current increases with time. The shape and temporal range of this behavior rules out the presence of parasitic capacitive effects.

A novel laser-printing method for the manufacturing of the backplane circuits of active-matrix liquid-crystal displays (AMLCD) is proposed and demonstrated. Xerographic toner is used as an etch mask for amorphous silicon (a-Si:H) and for the seeding of metal lines. We also demonstrate for the first time the direct-print patterning of silicon on ∼ 50 μm thick glass foil.

On the basis of our experimental studies of the temperature dependence of amorphous silicon thin film transistor current-voltage and capacitance-voltage characteristics, we have developed an analytical device model suitable for implementation in circuit simulators. This model describes the above-threshold (on) current and the subthreshold (off) current [1]. In addition, the model is able to incorporate changes in the distribution of localized states which arise from thermal and/or bias stress. In this paper, we identify the temperature-dependent parameters, which describe the temperature dependence of both the on and off currents, and we model the leakage current at large negative gate biases. The modeling results are in good agreement with our experimental data. We also discuss capacitance-voltage characteristics of amorphous silicon thin film transistors for varying gate lengths, temperatures, and frequencies. The measured capacitance-voltage characteristics show strong frequency dispersion, which is related to the trap-limited transport of carriers in the channel. The characteristic time constant, which determines when the channel capacitance becomes dependent on frequency, is on the order of the transit time calculated with the field-effect mobility and the electric field. The field-effect mobility takes into account carrier trapping by the localized states and is a function of gate voltage and temperature.

This work describes the deposition and characterisation of semi-insulating oxygen-doped silicon films for the development of high voltage polycrystalline silicon (poly-Si) circuitry on glass. The performance of a novel poly-Si High Voltage Thin Film Transistor (HVTFT) structure, incorporating a layer of semi-insulating material, has been investigated using a two dimensional device simulator. The semi-insulating layer increases the operating voltage of the HVTFT structure by linearising the potential distribution in the device offset region.

A glass compatible semi-insulating layer, suitable for HVTFT applications, has been deposited by the Plasma Enhanced Chemical Vapour Deposition (PECVD) technique from silane (SiH4), nitrous oxide (N2O) and helium (He) gas mixtures. The as-deposited films are furnace annealed at 600°C which is the maximum process temperature. By varying the N2O/SiH4 ratio the conductivity of the annealed films can be accurately controlled up to a maximum of around 10−7 Ω−1.cm−1 Helium dilution of the reactant gases improves both film uniformity and reproducibility. Raman analysis shows the as-deposited and annealed films to be completely amorphous. A model for the microstructure of these Semi-Insulating Amorphous Oxygen-Doped Silicon (SIAOS) films is proposed to explain the observed physical and electrical properties.

We developed a totally wet etch processing technology for the fabrication of inverted staggered amorphous silicon thin-film transistors (TFTs) and circuits. In this technology we take advantage of highly etch selective KOH and HF base solutions for amorphous silicon and silicon nitride layers. Our technology is simple, reproducible, fully compatible with positive photo-resist lithography techniques, and suitable for mass production of amorphous silicon TFT based circuits. Using this process, we fabricated thin film transistors which have an effective mobility of 0.83 cm2 V−1 s−1, threeshold voltage of 2V and on/off current ratio of 107. In this paper we discuss the details of our fabrication process and report on the chemical conditions of the etching and deposition processes.

The off currents in high performance a-Si:H TFT's were measured below 10−12 A. The Ioff-Vgs behavior is similar to that of a poly-Si TFT, in which the current increases rapidly with negative gate bias under a large drain bias while it stays almost constant under a small drain voltage. It seems the thermally-assisted tunneling via localized states occurs near the drain region as in the case of poly-Si TFT, although the current level is quite different. The off current change after negative bias stress at room temperature can be explained by the defect creation, but defects can be reduced by negative stress at 180 °C according to the defect pool model.

We evaluated the characteristics of a-Si:H/a-SiNx:H thin film transistors (TFTs), and of separately deposited a-Si:H films, as functions of the a-Si:H deposition power in a high-rate, large-area, 40 MHz PE-CVD system. TFT performance and a-Si:H film properties improve with decreasing power density and deposition rate. However, low defect density a-Si:H material was deposited at rates as high as 1500 Å/min. TFTs with gate nitride deposited at 1000 A/min show excellent I-V characteristics when the a-Si:H deposition power is low enough. The TFT electron mobility in the linear regime correlates well with the Urbach energy of the a-Si:H films, suggesting that the quality of the a-Si: H controls the performance of our TFTs.

Large two dimensional amorphous silicon image sensor arrays offer a new approach to electronic document input and x-ray imaging. The sensor array technology is now capable of image capture at greater than 10 frames/sec and with resolution of 200–400 spi. We describe our new high resolution imaging system, comprising a page-sized sensor array with nearly 3 million pixels, and the accompanying high speed read out and processing electronics. The key technological issues of pixel resolution, sensor fill factor, leakage currents and noise are reviewed. Measurements of a new array architecture are described, in which the sensor is formed as a single continuous film on top of the matrix addressing components.

The photoconductive gain mechanism in a-Si:H was investigated in connection with applications to radiation detection. Various device types such as p-i-n, n-i-n and n-i-p-i-n structures were fabricated and tested. Photoconductive gain was measured in two time scales: one for short pulses of visible light (< 1 μsec) which simulates the transit of an energetic charged particle, and the other for rather long pulses of light (1 msec) which simulates x-ray exposure in medical imaging. We used two definitions of photoconductive gain: current gain and charge gain which is an integration of the current gain. We found typical charge gains of 3 ∼ 9 for short pulses and a few hundred for long pulses at a dark current level of 10 mA/cm2. Various gain results are discussed in terms of the device structure, applied bias and dark current.