We have measured thermoplastic deformation in as-received, single-side polished, 4H-SiC wafers and also residual stresses in homoepitaxially grown epilayers on wafers by radius curvature measurements. The wafers studied had n-type resistivities of 0.010-0.011 ω-cm and p-type resistivities of 4.42, 4.72, 9.57 ω-cm. In a first thermal excursion to 900 °C in vacuum, the bow height of the bare substrates in all cases decreased with temperature. Upon cooling down, however, the bow heights remained largely unchanged from their values at 900 °C. A second cyclic excursion to 900 °C did not yield any significant change in the curvature, thus indicating that the substrates had thermoplastically deformed in the first heating cycle. Epilayers having nitrogen doping between 5 × 1017 and 2 × 1019 cm−3 grown on the n- and p-type substrates resulted in compressive stresses ranging between 190 and 400 MPa in the epilayers. Transmission electron microscopy (TEM) examination of the n-type epilayer (with doping levels of 5 × 1017 cm−3 and 5 × 1018 cm−3) on the n-type substrate, revealed bands of stacking faults (SFs) confined within the epilayers after the bicrystals were further annealed at 1150°C in nitrogen for thirty minutes. These doping levels are approximately one and two orders of magnitude below the reported threshold value of 3 × 1019 cm−3 previously suggested for the onset generation of SFs in annealed n-type 4H-SiC epilayers. The calculated residual stresses in all the epilayers were above the critical stress for the motion of dislocations above 1000 °C in 4H-SiC. Thus the SFs that form by glide of pre-existing partial dislocations may actually be stress induced and occur across a much wider range of doping levels. Therefore, it is possible that a significant mechanism for formation of the stacking faults and 3C bands observed in thermally treated 4H-SiC wafer is stress relief via the generation and motion of new and pre-existing partial dislocations on the basal planes of 4H-SiC.

Phenolic resin and tetraethoxysilane were used to prepare a binary carbonaceous silicon xerogel, the precursor of silicon carbide (SiC). By employing different additives in the sol-gel process, a series of xerogel precursors with differently chemical composition were obtained. Heating these xerogels to 1250°C, nanostructured β-SiC with various morphologies including nanowires, nanofibers, nanoparticles and mesoporous SiC were produced via carbothermal reduction. The preparation method of the xerogels was presented and the influences of different additives on the sol-gel process and the SiC formation were discussed in this paper.

Laboratory prototype SiC diodes are fabricated using a combination of gas immersion laser doping (GILD) and laser direct write (LDW) in situ metallization in a commercial SiC wafer. Trimethylaluminum (TMA) and nitrogen are the precursors used to produce p-type and n-type SiC, respectively. Using these techniques, a 150 nm p-type doped junction is fabricated in semiinsulating 6H-SiC and n-doped 4H-SiC wafers. Ohmic contacts are created by laser direct metallization producing carbon rich conductive phases in these doped materials. Alternatively an excimer laser can be used to create silicon rich Schottky contacts. The geometry of the diodes can be vertical or planar to the wafer surface and the laser processes are thought to reduce defect densities in the irradiated areas. These laser-processed diodes are intended for use in high temperature, high voltage and high frequency switching and sensing applications.

A Pd/AlN/SiC device was fabricated with a 550 Å thick AlN layer in between the SiC substrate and Pd gate. At fixed flow rate, the response to Hydrogen initially increases roughly linearly with concentration, but eventually becomes saturated. The magnitude of the response as well as the saturating concentration increase with temperature. At 120° C the response saturates around 60 ppm of H2 whereas at 250° C, the onset of saturation occurs at higher ppm. The magnitude of the response also increases with the total flow rate, up to a flow rate of 250 sccm beyond which it remains constant. In the linear region, the magnitude of the response increases by a factor of 4 between 120° and 250° C, at a flow rate of 250 sccm.

The defects associated with the implantation and diffusion of boron in silicon carbide have been studied using secondary ion mass spectrometry (SIMS) and photoluminescence (PL) imaging and spectroscopy. An n-type epitaxial SiC (1000) substrate was implanted with 2×1014 atoms/cm2 B and annealed to 1700°C. PL data was acquired before and after annealing, and following removal of various thicknesses of the sample by mechanical polishing. Thermal annealing generated a B diffusion profile measured by SIMS to extend to about 3 microns depth. After removing the diffused B layer, a PL spectral feature at 415nm disappeared, which is consistent with its previous identification as arising from donor-acceptor pairs (DAP). The D1 spectral features survived polishing, supporting previous suggestions that these features are intrinsic defects due to the di-interstitial (Ic-Ic or Isi-Isi) or di-vacancy (Vc-Vc or Vsi-Vsi) defects.

II-VI, Inc. is a commercial supplier of high-quality SiC substrates (including 2-inch and 3-inch diameter) for RF and power applications to the US market. Semi-insulating 6H-SiC single crystals, doped with vanadium and undoped (vanadium-free), as well as ntype 4H crystals have been grown using the PVT and Advanced PVT (APVT) growth techniques. The APVT process incorporates insitu synthesis and growth of of SiC crystal from Si and C precursors.

Grown 6H-SiC and 4H-SiC crystals have been extensively characterized with respect to their purity, crystal quality and electrical properties. COREMA resistivity maps demonstrate that V-compensated boules exhibited axially and radially uniform resistivity around 1011 ω.cm at room temperature. Undoped (V-free) wafers contained residual boron and nitrogen at levels below 1016 atoms/cm3, and demonstrated semi-insulating properties (resistivity between 106 and 1011 ω.cm) as a result of compensation by native point defects with deep levels in the bandgap. The undoped semi-insulating crystals grown by APVT contained boron and nitrogen at 1.9ω1015 cm−3 and 3.8.1015 cm−3, respectively.

High-quality 2-inch SiC wafers exhibited micropipe densities on the order of 10 cm−2 and dislocation density on the order of 104 cm−2.

A RESURF-type JFET is a suitable structure as a lateral switching device with a breakdown voltage of above 600 V for an inverter module which drives motors of an electric or hybrid automobile. In this study, 600 V RESURF-type JFETs were fabricated to investigate the operation and characteristics. The drift region between the drain and the source areas has a double RESURF structure to reduce the on-resistance. At first, small devices were fabricated. The width and length of the channel are 200 μm and 10 μm, respectively. The distance between the drain and the gate areas, which is the drift length, is 15 μm. The saturation current normally-off device is about 0.6 mA at a gate voltage of 3 V. The specific on-resistance is about 160mωcm2. The maximum breakdown voltage is 720 V. Next, large ones were fabricated. The width of the channel is 80 mm. The saturation current normally-on device is about 0.5 A at a gate voltage of 2 V. The specific on-resistance is about 200mωcm2. The maximum breakdown voltage is 250 V.

We report on the optical properties of defects introduced in epitaxial 4H-SiC by 2 MeV protons using photoluminescence spectroscopy. The near band edge characteristics of nitrogen-doped n-type 4H-SiC are present in the optical spectrum of the as-grown samples. Following a proton irradiation, the material is altered and the luminescence of the shallow centers is attenuated almost entirely with the emergence of deeper shallow traps at energies greater than 300 meV below the conduction band. Subsequent hightemperature thermal annealing of the material results in an increase in the emission spectrum at both the near band edge region (Eg = 3.25 eV) and between 2.65 and 2.95 eV. Recovery of the characteristic nitrogen-related peaks at the near band edge following high-temperature annealing is identified, but is not complete even at 1500 °C. In the deep trap region below 2.95 eV, activation of trap centers with annealing results in a sharp increase in the signal intensity of an irradiation-induced defect trap (2.90 eV) as well as the associated phonon replicas. Based on previous ion-implantation and other radiation studies in 4H-SiC, the emergence of the 2.90 eV defect complex and associated phonon replicas after high temperature anneal is the well known D1 photoluminescence. The observed lines in the D1 spectrum are due to exciton recombination at isoelectronic defect centers.

Cubic silicon carbide (3C-SiC) is a suitable semiconductor material for high temperature, high power and high frequency electronic devices, because of its wide bandgap, high electron mobility and high saturated electron drift velocity. The usage of Si substrates has the advantage of large area substrates for the growth of 3C-SiC layers. However, large lattice mismatch between 3C-SiC and Si (>20%) has caused the generation of defects such as misfit dislocations, twins, stacking faults and threading dislocations at the SiC/Si interface. Lateral epitaxial overgrowth (ELOG) of 3C-SiC on Si substrates using SiO2 has been reported to reduce the defect density. In this report, epitaxial growth of 3C-SiC on T-shape patterned (100) Si substrates has been investigated to reduce interfacial defects.

The device on Si substrates behaves as an MIS capacitor and the response to hydrogen is given by a shift of the capacitance vs. bias profile along the bias voltage axis, whereas the device on SiC behaves as a rectifying diode and the presence of hydrogen causes a shift of the forward current vs. voltage plot. The relatively large forward current, in both cases, indicates that there is measurable electrical transport across the AlN layer, but at the same temperature the turn on bias is different. Either structure contains two rectifying contacts in series, namely a Schottky contact between Pd and AlN and a heterojunction between AlN and the substrate.

High-dose aluminum-ion (Al+) implantation into 4H-SiC (11-20) and (0001) has been investigated. Surface morphologies of implanted (0001) samples were improved by annealing with a graphite cap. Implant-dose dependence and annealing-time dependence of electrical properties are examined by Hall-effect measurements. A low sheet resistance of 2.3 kΩ/sq. was obtained in (0001) by high-dose Al+ implantation at 500 °C with a dose of 3.0 × 1016 cm−2 and high-temperature annealing at 1800 °C for a short time of 1 min. In the case of (11-20), even room-temperature implantation brought a low sheet resistance below 2 kΩ/sq. after annealing at 1800 °C.

TDDB measurements of NMOS capacitor fabricated with 1200°C dry oxide with 1300°C N2O anneal were performed at 175°C and 300°C under high positive bias stress. The devices are biased into strong accumulation mode such that the field in the oxide is high enough to collect breakdown data in a reasonable period of time. We observe that at 175°C, a 100-year Mean Time to Failure (MTTF) is obtained at an electric field of 3 MV/cm in the oxide. The TDDB measurement has also been performed at 300°C where lifetime has been reduced by a few orders of magnitude, but with an acceptable 100-year MTTF. Recent reliability results on similarly oxidized MOSFETs have shown failures along the same trend as the n-type capacitors, indicating that MOSFETs and MOS capacitors can have similar reliability despite inherent processing and structural differences. PMOS capacitors fabricated with the aforementioned dry + N2O process as well as capacitors fabricated using the low DIT nitridation techniques show acceptable MTTF of 100 years at the nominal operating electric field of 3 MV/cm.

Surface treatment is a key technological parameter in the microelectronics technology and especially for SiC devices since high temperatures must be used for implanted impurities annealing and crystal damage recovery. In this work we take profit of a novel fine polishing process developed by NOVASIC to improve the electrical characteristics of Boron and Aluminium implanted Schottky diodes, which are surface quality highly sensitive devices. The mentioned fine polishing process allows to remove a layer thickness of 100nm to 3000nm on the surface of a processed SiC wafer, reducing the surface roughness to RMS of 1Å. The impact of this process on the electrical properties of the samples shows a general improvement of characteristics reproducibility, reduction of leakage current and improvement of breakdown of Boron implanted diodes.

Homoepitaxial films of 4H-SiC(1120) and 8° off-axis 4H-SiC(0001) have been grown and characterized. The number of domains and the range of full-width half-maxima values of the x-ray rocking curves of the [1120]-oriented wafers were smaller than the analogous values acquired from the (0001) materials. Hydrogen etching of the former surface for 5 and 30 minutes reduced the RMS roughness from 0.52 nm to 0.48 nm and to 0.28 nm, respectively; the RMS roughness for a 30 μm (1120) film was 0.52 nm. Micropipes in the substrates did not thread beyond the film-substrate interface. The separation distance between stacking faults was determined to be 10 μm by transmission electron microscopy. Hall mobilities and carrier concentrations of 12,200 cm2/Vs and 3.1×1014 cm−3 and 800 cm2/Vs and 7.4×1014 cm−3 were measured at 100°K and 300°K, respectively. Photoluminescence indicated high purity. 4H-SiC(1120) PiN devices exhibited average blocking voltages to 1344 V and a minimum average forward voltage drop of 3.94 V.

Deep level transient spectroscopy (DLTS) was used to study deep level defects in He-implanted n-type 6H-SiC samples. Low dose He-implantation (fluence ∼2×1011 ions/cm2) has been employed to keep the as-implanted sample conductive so that studying the introduction and the thermal evolution of the defects becomes feasible. A strong broad DLTS peak at 275K-375K (called signal B) and another deep level at EC-0.50eV were observed in the as-implanted sample. The intensity of the peak B was observed to linearly proportional to the logarithm of the filling pulse width, which is a signature for electron capture into a defect related to dislocation. After annealing at 500°C, the intensity of peak was significantly reduced and the remained signal has properties identical to the well known Z1/Z2 deep defects, although it is uncertain whether the Z1/Z2 exist in the as-implanted sample or it is the annealing product of the dislocation-related defect. The E1/E2 defect (EC-0.3/0.4eV) was not presence in the as-implanted sample, but was observed after the 300°C annealing.

We have studied the interaction of C60 with clean Si(111) and sub-monolayer Co covered Si(111) using scanning tunneling microscopy (STM) and X-ray photoelectron spectroscopy (XPS). Our STM results indicate that C60 has little mobility at room temperature (RT) on Co/Si(111). After annealing to 450 °C, STM images show a regular arrangement of partially decomposed C60. XPS reveals a partial decomposition of C60 on Co/Si(111) at 520 °C, and total decomposition to form a SiC-3×3 phase at 720 °C. These results show that Co catalyses C60 decomposition resulting in the formation of the ordered SiC-3×3 phase ∼200 °C below that on clean Si(111).

Single crystal 3C-SiC epitaxial layers have been grown on SOI substrates using low-pressure chemical vapour deposition (LPCVD). The SOI substrates consist of nominally 150 Å Si layers bonded to 100 mm poly 3C-SiC substrates using direct wafer bonding and SOI film transfer techniques. Miscut Si(100) films were incorporated into the wafer bonding process for the first time in an effort to further reduce anti-phase domain formation in the 3C-SiC films. The Si films were transferred from Si(100) wafers miscut 4° toward the (110) direction. For growth of 3C-SiC layers, a two-step process is needed. First the Si is carbonized using propane mixed in a hydrogen carrier gas to convert the surface to SiC at atmospheric pressure. Next SiC growth is conducted by the addition of silane into the gas mix and a reduction of the process to 150 Torr. Previous characterization of these films via SEM and XRD indicated that the films were single crystal and oriented with respect to the starting Si bonded film. In this work we present results of TEM analysis of these films which show details of the atomic structure at the 3C-SiC/poly-crystalline SiC interface where a thin (6 nm thick) amorphous region has been detected, likely due to SiO2 used to wafer bond the Si film to the poly substrate. A detailed study of this material system is presented with the aim of providing feedback for possible improvements in the 3C-SiC growth process.

Growth technique for thick SiC epilayers with a reduced micropipe density has been developed in a vertical hot-wall CVD reactor. Micropipe closing by growing an epilayer is possible with a nearly 100% probability for 4H-SiC substrates oriented (0001) and (000-1) off-cut towards either [11-20] or [1-100]. By applying the micropipe closing technique, a high-performance Schottky barrier diode (SBD) was demonstrated on a substrate including micropipes. Growth of low-doped and thick SiC epilayers is also possible with a good morphology at a high growth rate, and 14.4 kV blocking performance was demonstrated using a 210 μm-thick epilayer. Epitaxial growth on (000-1) substrates with low doping and a low epi-induced defect density was also demonstrated. Deep centers and impurities were investigated to determine the effective lifetime killer of the epilayers. Dislocations and stacking faults in epilayers grown on 4H-SiC substrates off-cut towards different directions were also investigated.

Electronic devices based on single crystal SiC represent a good choice for a variety of new high temperature, high power electronics applications. The challenge is to develop a package that is resistant to thermal degradation in harsh environments. Conditions are extreme and this all but rules out only a handful of materials and materials systems. Polycrystalline SiC is the material that we have chosen to study as a suitable package and materials suitability/compatibility has been considered on several levels.

The performance enhancements offered by the next generation of SiC high power devices offer potential for enormous growth in SiC power device markets in the next few years. For this growth to occur, it is imperative that substrate and epitaxial material quality increases to meet the needs of the targeted applications. We will discuss the status and requirements for SiC substrates and epitaxial material for power devices such as Schottky and PiN diodes. For the SiC Schottky device where current production is approaching 50 amp devices, there are several material aspects that are key. These include; wafer diameter (3-inch and 100-mm), micropipe density (<0.3 cm−2 for 3-inch substrates and 16 cm−2 for 100-mm substrates), epitaxial defect densities (total electrically active defects <1.5 cm−2), epitaxial doping and epitaxial thickness uniformity. For the PiN diodes the major challenge is the degradation of the Vf characteristics due to the introduction of stacking faults during the device operation. We have demonstrated that the stacking faults are often generated from basal plane dislocations in the active region of the device. Additionally we have demonstrated that by reducing the basal plane dislocation density, stable PiN diodes can be produced. At present typical basal plane dislocation densities in our epitaxial layers are 100 to 500 cm−2; however, we have achieved basal plane dislocation densities as low as 4 cm−2 in epitaxial layers grown on 8° off-axis 4H-SiC substrates.