Forward and reverse current – voltage (I–V) characteristics of N and P-type Schottky diodes on 6H-SiC are compared in a temperature range of room temperature to 550K. While the room temperature I–V characteristics of the N-type Schottky diode after turn-on is more or less linear up to ∼ 100 A/cm2, the I–V characteristics of the P-type Schottky diode shows a non-linear behavior even after turn-on, indicating a variation in the on-state resistance with increase in forward current. For the first time it is shown that at high current densities (> 210 A/cm2) the forward voltage drop across P type Schottky diodes is lower than that across N type Schottky diodes on 6H-SiC. High temperature measurements indicate that while the on-state resistance of N type Schottky diodes increases with increase in temperature, the on-state resistance of P type Schottky diodes decreases with increase in temperature until a certain temperature. While the N-type diodes seem to have soft breakdown characteristics, the P-type diodes exhibit more or less abrupt breakdown characteristics.

Bipolar devices made with SiC offer 20–50X lower switching losses as compared to conventional semiconductors, and a comparable on-state voltage drop at sufficiently high current densities. To exploit the tremendous advantages offered by SiC for bipolar power devices, it is important to understand the relevant voltage/current range, fundamental limits and technological challenges in order to develop this technology commercially. The opportunity of operating a device at a high current density (>300 A/cm2) to increase total current with reasonable yield, the poor reliability of MOS at high temperatures, and the relatively low channel mobilities obtained in 4H-SiC MOSFETs may make certain bipolar devices more attractive even as low as 1700 V. The total power loss in various bipolar devices is analyzed and compared to fundamental operational limits in order to find the applicability of various devices to advanced applications.

A comparative study of Pt and Pt/Si contacts to p-type 6H-SiC in terms of various processing conditions and interlayer specifications was performed. Deposition temperature, the thickness of the Si layer, and B-dopant incorporation in the Si were found to significantly affect the specific contact resistivity (SCR) values. In addition, pre-etching of the SiC surface in SF6 + Ar was found to consistently reduce the SCR's. The lowest average SCR values were 3 × 10−5 Ωcm2 for Pt/Si/SiC contacts deposited on pre-etched SiC surfaces (7.0 × 1018 cm−3 doping concentration) and annealed at 1100 °C for 5 min.

Aluminum-titanium contacts also showed dependence on the thicknesses of the Al and Ti layers and on the locations of the layers. Differences in both the SCRs and surface morphology are presented.

Compensating impurities affect the device performance but still the fundamental knowledge of this effect in SiC is poor. We demonstrate that the optical properties are affected by compensation effects between the nitrogen donor and aluminium acceptor in 4HSiC epilayers. As demonstrated using low-temperature photoluminescence measurements, the interaction occurs between the impurity bound excitons caused by changes in the aluminium concentration while the nitrogen concentration is constant. The variation is observed over two orders of magnitude in the aluminium concentration. The interplay is also observed in cathodoluminescence measurements between the band edge luminescence and nitrogen-aluminium donor-acceptor pair emission. These observations may be possible to utilize for a non-destructive characterization of compensated epilayers.

Fabrication and evaluation of high voltage n-type 4H-SiC Schottky barrier diodes (SBDs) using 27μm thick epitaxial layers were presented. To achieve the ideal value of the breakdown voltage, various parameters of junction termination extension (JTE) were investigated. We concluded that the termination of triple rings with the concentrations of 6×1017, 3×1017, 1.5×1017cm−1 outwardly was best with the simulations. The SBDs with this termination showed the blocking voltage up to 3.4kV, which is almost the ideal value. We also investigated the distribution of leakage currents at -600V in SBDs with various diameters up to 4mm. High yield was obtained in the SBDs with the diameters below 2mm. The SBDs with high leakage currents showed the excess currents in the low forward voltage region and lots of bright spots could be observed by optical beam induced current analysis.

Based upon graphite mask, selective aluminum/boron doping of SiC by thermal diffusion has been successfully realized in a temperature range of 1800 to 2100°C. Secondary ion mass spectrometry (SIMS) was used to identify the doping profiles, which showed very high aluminum concentration (5×1019 cm−3) near the surface and linearly graded boron profile up to several micrometers in depth. Hall-effect measurement was also employed to obtain the carrier concentration, which showed more than 1019 cm−3 carrier concentration at room temperature. Cathodoluminescence (CL) image clearly illustrated the locally diffused pattern. In addition, planar p-n diodes based upon this technique were fabricated and current-voltage (I-V) characteristics were measured. Excellent rectification property has been obtained. Built-in voltage of 2.9 V in the formed p-n junction was obtained by capacitance-voltage (C-V) measurement.

The density of interface states Dit at SiC/SiO2 interfaces of different SiC polytypes (4H-, 6H- and 15R-SiC) is monitored and the origin of these states is discussed. The hydrogenation behavior of interface states in the temperature range from 250°C to 1000°C is studied by C-V and G-V investigations. The strong increase of Dit close to the 4H-SiC conduction band is attributed to defects located in the oxide (so-called “Near Interface Traps”).

This paper presents a review of new results obtained by a combination of first-principles theory, Z-contrast imaging, and electron-energy-loss spectroscopy in the context of a broader experimental/theoretical program to understand and control the atomic-scale structure of SiCSiO2 interfaces. The ultimate purpose is to achieve low interface trap densities for device applications. Results are given for global bonding arrangements in comparison with those of the Si-SiO2 interface, the mechanism of the oxidation process, the nature of possible interface defects and their passivation by N and H, and the formation and dissolution of C clusters in SiO2 during oxidation and reoxidation.

Positron affinity calculations performed by a first-principles approach based on density functional theory reveal, contrary to many other semiconductors, that free positrons and positronium atoms can escape from SiC. It is found that the treatment of the electronpositron interaction plays a crucial role when calculating the annihilation characteristics. These characteristics originating from both valence and core electrons, combined with the corresponding measurements, yield a very useful tool for surface studies and point defect identification in the bulk. Calculations will be compared with available experimental data.

We have investigated the effect of polytype and oxidation condition on the temperature dependence of channel mobility and threshold voltage in 4H- and 6H-SiC MOSFETs. The behaviors of the channel mobility are apparently different for 4H- and 6H-SiC MOSFETs. In contrast to the polytype effect, dry and wet oxidation samples have almost similar channel mobilities. The variation of the threshold voltage with temperature is proportional to the number of the interface states near the conduction band extracted from n-type MOS capacitors. Therefore, we argue that the distribution of the interface states near the conduction band in p-type SiC MOS structure can be represented by that in n-type SiC MOS structure. Although the oxidation condition varies the distribution of the interface states in the energy range between 0.2 and 0.4 eV from the conduction band, it has little influence on the channel mobility.

We have succeeded in pulsed laser annealing of N+ ion-implanted n-type 6H-SiC for increasing the carrier density near surface in order to decrease contact resistance, which induces little redistribution of implanted impurities after laser irradiation. By repeated laser irradiation at low energy density, the ion–implanted impurities were electrically activated without melting the surface region. SiC substrates with impurity concentration of 2×1018 /cm3 were implanted with 30 keV N+ ions with dose of 4.7×1013/cm2. After pulsed laser annealing, a contact resistance was measured to be 5.7×10−5 Ωcm2 using Al electrode on the N+ -implanted layer.

The implementation of SiC based sensors and electronics for operation in chemically harsh, high temperature environments depends on understanding the SiO2/SiC interface in field effect devices. We have developed a technique to fabricate wedge polished samples (angle ∼ 1×10−4 rad) that provides access to the SiO2/SiC interface via a surface sensitive probe such as xray photoelectron spectroscopy (XPS). Lateral scanning along the wedge is equivalent to depth profiling. Spatially resolved XPS images of the O 1s and Si 2p core levels were obtained of the interfacial region. Samples consist of device-quality thermally grown oxides on 4H-SiC single crystal substrates. The C 1s spectrum suggests the presence of a graphitic layer on the nominally bare SiC surface following thermal oxidation.

The effects of Chem-Mechanical Polishing (CMP) and Rapid Thermal Annealing (RTA) on n-type 4H:SiC samples doped with nitrogen were investigated using Raman scattering and X-ray Phtoelectron Spectroscopy (XPS a.k.a. ESCA) measurements. A comparison of the Raman spectra from Mechanically Polished (MP) SiC annealed at 600°C and 800°C displays a frequency shift in the coupled plasmon LO-phonon mode. Since the coupled mode frequency is a direct measure of the free carrier concentration, this observation may suggest the removal of polishing induced carrier traps with increasing annealing temperature. The CMP samples did not show this frequency shift, thereby indicating that such polishing traps were not created in that process. The Si-peak observed in the XPS spectra of the unannealed CMP sample indicates primarily a Si-C bonding, while that for the MP sample is more complex, indicating other bonds beside Si-C. Drastic changes in O, C, Si surface content were observed for annealing between 1000°C and 1100°C. The peaks in the XPS spectra associated with the chemical environment for C, O, and N are complex and may be explained as silicon oxycarbide type structures near the surface or possibly around the interface of the SiC substrate with a thin surface oxide layer.

A number of F2-based plasma chemistries (NF3, SF6, PF5 and BF3) were investigated for high rate etching of SiC. The most advantageous of these is SF6, based on the high rate (0.6 μm · min−1) it achieves and its relatively low cost compared to NF3. The changes in electrical properties of the near-surface region are relatively minor when the incident ion energy is kept below approximately 75 eV. At a process pressure of 5 mTorr, the SiC etch rate falls-off by ∼15 % in 30 μm diameter via holes compared to larger diameter holes (> 60 μm diameter) or open areas on the mask.

The aim of this work is to study the origin of parasitic phenomena in the output characteristics of 4H-SiC MESFETs on semi-insulating (SI) substrates with various buffer layers. Ids-Vds measurements as a function of temperature have first been performed. Different parasitic effects such as kink effect, hysteresis effect when the gate voltage is successively increased or decreased, or changes in the output characteristics after a high drain polarization are presented. Random Telegraph Signal (RTS) measurements and frequency dispersion of the output conductance have next been realized. From the obtained results, we propose that the parasitic effect on the output characteristics are correlated with the presence of deep levels located near the semi -insulating substrate interface. The main observed trap is tentatively attributed to the presence of Vanadium in the SI substrate.

Thermodynamically stable, low specific contact resistance electrical contacts to SiC are essential to the application of such devices in high power or high temperature applications. However, thermal budgets impose processing constraints due to interfacial reactions and dopant profiles during device fabrication. Nickel disilicide (NiSi2) is useful for metallization of SiC, as stable contacts can be formed on SiC by reacting a fugitive layer of amorphous silicon (a-Si) with sputtered nickel at 300°C. NiSi2 forms directly upon reacting nickel with a-Si; this is not the case when nickel is reacted with crystalline silicon, where more nickel-rich silicides form first. Specific contact resistances as low as 5.6×10−5 Ωcm2 have been measured using NiSi2 circular TLM contacts so formed on APCVD 3C-SiC thin films deposited on a silicon wafer.

The differences of secondary defects between B+ and Al+ implanted layers in high-energy implantation were investigated. At the same volume concentration of implanted ion, density of secondary defects in Al+ implanted layer is higher than that in B+ implanted layer. On the contrary, mean defect size in B+ implanted layer is larger than that in Al+ implanted layer. The structure of secondary defect is thought to be a dislocation loop formed by an extra Si-C layer or localized lattice strain correlated to agglomerated interstitials. The amount of interstitials used for secondary defect formation is estimated. It almost coincides the same amount of implanted ions, and this correlation doesn't depend on ion species. B+ and Al+ implanted layers have different activation energy for secondary defect formation. This result means that they have different agglomerating mechanism of interstitials, which cause the differences of defect size and density between them.

6H- and 4H- SiC crystals grown on the Si-face were chemically etched on the as-grown (virgin) surface and the C-face (sliced side). The etching of both the surfaces revealed a strong relationship between a variety of etch pits and the morphological features of the grown boule surface. Several types of etched patterns were revealed. On the Si face, we observed small, medium, and large hexagonal shaped pits and a linear array of small etch pits. However, the C face contained only small pits and a linear array of small pits.

We observed individual or group of dislocations that were connected from the Si face to the opposite C face of the wafer. Also, etch pit lines oriented along specific crystallographic directions were seen.

Our experimental observations have provided a physical basis to explain the generation of defects in SiC. An analysis of our observations show that a correlation exists between the distribution of different size etch pits and the condition of the crystal growth process.