We demonstrate that picosecond ultrasonics provides detailed information on the structure and properties of patterned arrays of copper fine lines used in silicon chip interconnections. In this method, the sample surface is momentarily heated several °C using a pump laser beam, and the transient change in the optical reflectivity is measured by a probe laser beam. Measurements of the optical reflectivity are made on time scales ranging from picoseconds to nanoseconds, revealing information on electronic, acoustic and thermal properties. We have applied this method to samples consisting of copper line arrays of 0.4 µm linewidth, 0.65 µm pitch and 0.35 µm depth in SiO2 on silicon wafers. For comparison, we examined the picosecond ultrasonic response of 200 nm-thick blanket copper thin films. The patterned Cu lines are found to have long-term oscillations at frequencies of 4.39 and 8.29 GHz with lifetimes at least 10 times longer than the oscillations in the blanket Cu film. A two-dimensional mechanical analysis was developed which uses as input parameters the dimensions and sound velocities of the materials in the sample, and finds the normal mode frequencies and displacements. The main vibrational modes are identified and described for the patterned lines, and the simulations confirm that the lowest frequency modes have very small damping coefficients. Also, the time-dependent signal is shown to reveal details of interface layers and integrity of the copper/liner interface.

New low-dielectric-constant inter-level dielectrics are being investigated as alternatives to SiO2 for future integrated circuits. In general, these materials have very different mechanical properties from SiO2. In the standard model, electromigration-induced stress evolution caused by changes in the number of available lattice sites in interconnects is described by an effective elastic modulus, B. Finite element calculations have been carried out to obtain B as a function of differences in the modulus, E, of interlevel dielectrics, for several stress-free homogeneous dilational strain configurations, for several line aspect ratios, and for different metallization schemes. In contradiction to earlier models, we find that for Cu-based metallization schemes with liners, a decrease in E by nearly two orders of magnitude has a relatively small effect on B, changing it by less than a factor of 2. However, B, and therefore the reliability of Cu interconnects can be strongly dependent on the modulus and thickness of the liner material.

Spontaneous deposition of copper seed layers from metal bearing organic based solutions onto sputter deposited titanium, titanium nitride, and tantalum diffusion barrier thin films has been demonstrated. Based on electrochemically driven cementation exchange reactions, the process was used to produce adherent, selectively deposited copper metal particulate films on blanket and patterned barrier metal thin films on silicon substrates. The organic solution deposited copper films were capable of acting as seed layers for subsequent electrolytic and electroless copper deposition processes using standard plating baths. Electroless and electrolytic copper films from 0.1µm to 1.0µm thick were produced on a variety of samples on which the organic solution copper acted as the initial catalytic seed layer. The feasibility of using organic solution deposited palladium as a seed layer followed by electroless copper deposition has also been demonstrated. In addition, experiments conducted on patterned barrier metal samples with exposed areas of dielectric such as polyimide indicated that no organic solution copper or palladium deposition occurred on the insulating materials.

HSQ (hydrogen silsesquioxane) is one of the promising low-k materials used in VLSI technology as an intra-metal dielectric to reduce capacitance-related issues. Like any other dielectrics, the integration of HSQ in multilevel interconnect schemes has been of considerable importance. In this study, the compatibility of HSQ with different nitride barrier layers, such as PVD and CVD TiN, PVD TaN, and CVD W2N, has been investigated by using a variety of techniques. The refractory metal barriers, Ti and Ta, are also included for a comparison. The degradation of HSQ films indicates a strong underlying barrier layer dependence. With CVD nitrides or refractory metals as barrier, HSQ exhibits a better structural and property stability than that with PVD nitrides. The possible mechanisms have been discussed to account for these observations.

A new CVD process is described for depositing conformal layers containing tungsten, tungsten nitride or tungsten oxide. A film of tungsten metal is deposited by vaporizing liquid tungsten(0) pentacarbonyl 1-methylbutylisonitrile and passing the vapors over a surface heated to 400 to 500 °C. This process can be used to form gate electrodes compatible with ultrathin dielectric layers. Tungsten nitride films are deposited by combining ammonia gas with this tungsten-containing vapor and using substrates at temperatures of 250 to 400 °C. Tungsten nitride can act as a barrier to diffusion of copper in microelectronic circuits. Tungsten oxide films are deposited by adding oxygen gas to the tungsten-containing vapor and using substrates at temperatures of 200 to 300 °C. These tungsten oxide films can be used as part of electrochromic windows, mirrors or displays. Physical properties of several related liquid tungsten compounds are described. These low-viscosity liquids are stable to air and water. These new compounds have a number of advantages over tungsten-containing CVD precursors used previously.

We have studied the effect of texture (X-ray diffraction pole figures) and grain morphology (Focus Ion Beam cross-sections) on the electromigration performances of copper damascene interconnects. Three different metallizations have been characterized : Chemical Vapor Deposition copper deposited on TiN (process A) and electroplated copper deposited either on Ta (process B) or TaN (process C). The reliability performance of these interconnects has been evaluated using both Wafer Level Reliability (WLR) and Package Level Reliability (PLR) tests on 4 and 0.6 νm wide lines using single metal level test structures. On the basis of the activation energy values and failure analysis observations, we concluded that interfacial diffusion plays a key role in the electromigration phenomenon for processes B and C whereas grain boundaries seem to be the active diffusion path for process A. The existence of several failure mechanisms during electromigration tests (interfacial or grain boundary diffusions), the impact of the damascene architecture on microstructure (sidewall textures and non columnar grain shapes) and the copper propensity for twinning seem to mask the impact of texture on the electromigration reliability of copper damascene interconnects.

Thin film properties of hydrogen silsesquioxane (HSQ) cured at different temperature under N2 and H2/N2 ambients have been studied. In this study, it was found that compared to an N2 ambient, film curing in an H2/N2 ambient will impact HSQ properties when the temperature is 400°C – 500°C. H2/N2 ambient can be used to minimize the dielectric constant while increasing modulus of the films. The data indicates that H2 can minimize the oxidation of the HSQ films and maintain the dielectric properties.

Low-k dielectric films have been developed using a new silsesquioxane based chemistry that allows both the electrical and mechanical properties to be tuned to specific values. By controlling the composition and film processing conditions of spin-on formulations, dielectric constants in the range 1.5 to 3.0 are obtained with modulus values that range from 1 to 30 GPa. The modulus and dielectric constant are tuned by controlling porosity, which varies from 0 to >60%, and final film composition which varies from HSiO3/2 to SiO4/2. The spin-on formulation includes hydrogen silsesquioxane resin and solvents. Adjusting the ratio of solvents to resin in the spin-on formulation controls porosity. As-spun films are treated with ammonia and moisture to oxidize the resin and form a mechanically self-supporting gel. Solvent removal and further conversion to a more “silica-like” composition occur during thermal curing at temperatures of 400 to 450°C. The final film composition was controlled through both room temperature oxidation and thermal processing. Final film properties are optimized for a balance of electrical, mechanical and thermal properties to meet the specific requirements of a wide range of applications. Processed films exhibit no stress corrosion cracking or delamination upon indentation, with indenter penetration exceeding the film thickness, and followed by exposure to water at room temperature. Films also exhibit high adhesive strength (> 60MPa) and low moisture absorption. Processing conditions, composition and properties of thin are discussed.

The integrated CVD-PVD Al plug process was successfully applied to a sub-quarter micron device for the simultaneous formation of plugs and wires. The effects of the underlayer on the via filling and the microstructure of the CVD-PVD Al films were investigated. Three types of underlayers were examined in this work: the Ti film deposited by the ionized PVD (I-PVD) method, the MOCVD TiN film stacked on the I-PVD Ti film, and the PVD Al film deposited on the I-PVD Ti film. Excellent via filling was achieved by employing the MOCVD TiN/I-PVD Ti or the PVD Al/I-PVD Ti as an underlayer. When only I-PVD Ti film was used as an underlayer, complete via filling was not obtained, because the CVD Al film sealed the top of vias. The CVD-PVD Al film deposited on the PVD Al/I-PVD Ti underlayer also showed excellent crystallographic texture of Al <111> and surface morphology, which is superior to those of the CVD-PVD Al film deposited on the MOCVD TiN/I-PVD Ti underlayer.

With decreasing geometries of metal interconnects the demands on metallization reliability increase rapidly. In addition to electromigration, stress-induced voiding becomes a major problem, influencing lifetime and functionality of integrated circuits. This paper summarizes our studies on stressmigration behavior of various AlCu-multilevel metallizations. A model for an estimation of the median time to failure is presented.

Tantalum (Ta) thin films of 35 nm thickness were investigated as diffusion barriers as well as adhesion-promoting layers between Cu and SiO2 using X-ray diffractometry (XRD), Scanning electron microscopy (SEM), Auger electron spectroscopy (AES) and X-ray photoelectron spectroscopy (XPS). After annealing at 600°C for 1h in vacuum, no evidence of interdiffusion was observed. However, XPS depth profiling indicates that elemental Si appears at the Ta/SiO2 interface after annealing. In-situ XPS studies show that the Ta/SiO2 interface was stable until 500°C, but about 32% of the interfacial SiO2 was reduced to elemental Si at 600°C. Upon cooling to room temperature, some elemental Si recombined to form SiO2 again, leaving only 6.5% elemental Si. Comparative studies on the interface chemical states of Cu/SiO2 and Ta/SiO2 indicate that the stability of the Cu/Ta/SiO2/Si system may be ascribed to the strong bonding of Ta and SiO2, due to the reduction of SiO2 through Ta oxide formation.

NMOS and PMOS transistors of various (W/L) ratios, down to 0.24µm channel length, have been used to investigate the effects of copper diffusion (from the backside) on their electrical parameters. A thin layer of copper film was deposited on the back surface of the wafer. Over 10 hours of annealing at 4000C was carried out. Electrical parameters such as the threshold voltage (VT0), the drain saturation current (IDsat) and the off-current (Ioff), for transistors, and the leakage current for large diodes were measured. Secondary Ion Mass Spectroscopy (SIMS) was used to monitor the copper diffusion. Even after 10 hours of annealing at 400°C, electrical parameters of both NMOS and PMOS devices and leakage currents of diodes showed no significant degradation.

Highly porous silica films with pore size in the nanometer scale are being extensively studied as potential candidates for interlevel dielectrics. Because these dielectric materials appear in the form of thin films with a thickness of only several thousand Angstroms, conventional techniques are difficult to be readily applied to study their structure and porosity. We employed small angle scattering in the grazing incidence geometry in this study. Using high resolution xray beamline with synchrotron radiation source, we demonstrate that the small angle x-ray scatteirng (SAXS) data of the porous films can be obtained. The structure of sol-gel derived silica - xerogel films on silicon substrate studied by specular reflectivity and grazing incidence small angle x-ray scattering (GISAXS) will be presented.

We report a comparison of the room temperature recrystallization of electroplated (EP) copper in blanket films as a function of thickness measured by focused ion beam (FIB) microscope images and sheet resistance measurements. Both sets of data show an increase in rate with film thickness from 0.75νm up to 5νm, while little recrystallization is observed in films thinner than 0.75νm. Interestingly, the recrystallization rates from FIB analysis are consistently faster than those from the sheet resistance measurements. These data suggest that the recrystallization is initiated close to the top surface of the EP Cu film, but that in thinner films a high surface-to-volume ratio allows surface inhibition or pinning to retard the transformation. A Johnson-Mehl-AvramiKolmogorov (JMAK) analysis of the two data sets yields unusually high values for the Avrami exponent μ of up to 7 for the FIB data, while lower values of around 4 are obtained for the sheet resistance data. X-ray diffraction pole figures of the films have also been collected and correlations between the crystallographic texture, film thickness and recrystallization are discussed.

The electromigration resistance of simple straight-line interconnects is usually used to estimate the reliability of complex integrated circuits. This is generally inaccurate, and overly conservative at best. The shapes and connectedness of interconnects is not accounted for in standard reliability assessments. We have identified the interconnect tree as the fundamental reliability unit. An interconnect tree consists of connected conducting line segments lying within a single layer of metallization, and terminating at two or more nodes at which there is a diffusion barrier such as a W-filled via. We performed electromigration experiments on the simplest tree structures, such as ‘L’- and ‘T’-shaped interconnects, as well as straight lines with an additional via in the middle of the line, passing currents of different magnitudes and directions through the limbs of the trees. We found that metal limbs ending in other limbs can act as reservoirs for electromigrating metal atoms. Passive reservoirs, which are limbs that do not carry electrical current, are generally beneficial for reliability, whereas limbs that do carry electrical current, called active reservoirs, can be beneficial or detrimental, depending on the direction and magnitude of the current in the reservoir. However, our experiments show that bends in interconnects do not affect their reliability significantly. We also found that the reliability of an interconnect tree can be conservatively estimated by considering void-growth and void-nucleation-limited failures at the most heavily stressed junction in the tree, which can be found by analyzing the geometry and current configuration. Our experimentally verified model for tree reliability can be used with layout tools for reliability-driven computer-aided design (RCAD), through ranking of the reliabilities of trees in order to identify areas at risk from electromigration damage.

Alcogels, aerogel precursors, were prepared by hydrolysis and condensation of the metal alkoxide tetraethylorthosilicate and were catalyzed by both acids and bases, according to a standard reaction. Alcogel solution was spin coated onto p-type silicon wafers and fluid extraction was achieved in an uncontrolled (room temperature, atmospheric pressure) environment. Film porosity was retained through surface modification and/or low vapor pressure solvent techniques. The microstructure and electronic properties of the resulting films were evaluated using non-contact atomic force microscopy (nc-AFM), cross sectional scanning electron microscopy (SEM), and transmission electron microscopy (TEM). Metal insulator semiconductor (MIS) devices were prepared and current-voltage and capacitance-voltage measurements were obtained from these devices. Annealing studies reveal a dramatic temperature dependent effect on both the microstructure and electronic properties of the porous silica films.

The via electromigration(EM) reliability of aluminum(Al) dual-damascene interconnects by using Niobium(Nb) new reflow liner is described. It has been found that the via EM lifetime was improved by introducing low-k organic spin on glass(SOG)-passivated structure than the conventional TEOS-SiO2/SiN-passivated structure. Higher EM activation energy of 1.08 eV was obtained for the SOG-passivated structure than the conventional TEOS-passivated structure of 0.9 eV, even though no significant Al micro-crystal structure difference was found for both structures. It has been turned out that the low-k SOG material has the 1/7 Young's modulus (8 GPa) of TEOS-SiO2 (57 GPa) or thermal SiO2(70 GPa). The small Young's modulus means that SOG is more elastically deformable and/or softer than TEOS or thermal SiO2. This elastic deformation of the low-k SOG could retard the tensile stress evolution due to the Al atom migration near the cathode via, and elongated the time until the Al interconnect tensile stress exceeds the critical stress value for void nucleation. It has been concluded that the small-RC and reliable multi-level Al interconnect can be realized by the Nb-liner reflow-sputtered process with soft and low-k SOG dielectric materials.

Low dielectric constant, nanoporous hydrogen silsesquioxane (HSQ) films were prepared using hybrid templating method by addition of a sacrificial labile polymer, polybutadiene (PB). Thermal gravimetric analyzer (TGA) was employed to monitor the decomposition behavior of HSQ-PB films. Curing of HSQ and decomposition of PB were performed by a two-stage thermal treatment to obtain a defect-free film. The porosity level and pore morphology of the resultant porous films were found to be dependent upon thermal treatment conditions applied.

We present here a method for fabrication of air-gaps between Cu-interconnects to achieve low intralevel dielectric constant, using a sacrificial polymer as a ‘place holder’. IC compatible metallization and CMP processes were used in a single damascene process. The air-gap occupies the entire intralevel volume between the copper lines with fully densified SiO2 as the planer interlevel dielectric. The width of the air-gaps was 286 nm and the width of the copper lines was 650 nm. The effective intralevel dielectric constant was calculated to be 2.19. The thickness of the interlevel SiO2 and copper lines were 1100 nm and 700 nm, respectively. Further reduction in the value of intralevel dielectric constant is possible by optimization of the geometry of the metal/air-gap structure, and by use of a low k interlevel dielectric material.

In this method of forming air-gaps, the layer of sacrificial polymer was spin-coated onto the substrate and formed into the desired pattern using an oxide or metal mask and reactive-ion-etching. The intralevel Cu trench is then inlaid using a damascene process. After the CMP of copper, interlevel SiO2 is deposited by plasma-CVD. Finally, the polymer place-holder is thermally decomposed with the decomposition products permeating through the interlevel dielectric material. The major advantages of this method over other reported methods of formation of air-gaps are excellent control over the geometry of the air-gaps; no protrusion of air-gaps into the interlevel dielectric; no deposition of SiO2 over the side-walls, and no degradation of the interlevel dielectric during the formation of air-gap.

An electromigration study has determined the lifetime characteristics and failure mode of dual-damascene Cu/oxide interconnects at temperatures ranging between 200 and 325 °C at a current density of 1.0 MA/cm2. A novel test structure design is used which incorporates a repeated chain of “Blech-type” line elements. The large interconnect ensemble permits a statistical approach to addressing interconnect reliability issues using typical failure analysis tools such as focused ion beam imaging. The larger sample size of the test structure thus enables efficient identification of “early failure” or extrinsic modes of interconnect failure associated with process development. The analysis so far indicates that two major damage modes are observable: (1) via-voiding and (2) voiding within the damascene trench.