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Backside Copper Contamination Issues in CMOS Process Integration – A Case Study

Published online by Cambridge University Press:  17 March 2011

K. Prasad ,
K.C. Tee ,
L. Chan  and
A. K. See
K. Prasad
Affiliation:
School of Electrical & Electronic Engineering Nanyang Technological University Nanyang Avenue, Singapore 639798
K.C. Tee
Affiliation:
School of Electrical & Electronic Engineering Nanyang Technological University Nanyang Avenue, Singapore 639798
L. Chan
Affiliation:
R&D Department Chartered Semiconductor Manufacturing Limited 60 Woodlands Industrial Park Street II, Singapore 738406
A. K. See
Affiliation:
R&D Department Chartered Semiconductor Manufacturing Limited 60 Woodlands Industrial Park Street II, Singapore 738406
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Abstract

NMOS and PMOS transistors of various (W/L) ratios, down to 0.24µm channel length, have been used to investigate the effects of copper diffusion (from the backside) on their electrical parameters. A thin layer of copper film was deposited on the back surface of the wafer. Over 10 hours of annealing at 4000C was carried out. Electrical parameters such as the threshold voltage (VT0), the drain saturation current (IDsat) and the off-current (Ioff), for transistors, and the leakage current for large diodes were measured. Secondary Ion Mass Spectroscopy (SIMS) was used to monitor the copper diffusion. Even after 10 hours of annealing at 400°C, electrical parameters of both NMOS and PMOS devices and leakage currents of diodes showed no significant degradation.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 612: Symposium D – Materials, Technology & Reliability for Advanced Interconnects.. , 2000 , D8.4.1
Copyright
Copyright © Materials Research Society 2000

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