The processes occuring in thin films, in particular such as silicide formation processes, are rather difficult to control using analytical measurements. Such processes are widely used for the formation of metallization layers and usually require the precise control of film thickness, atomic composition, atomic distribution profiles, phase composition and electric resistance 1. The absence of model concepts of the process of silicide formation hinders the wide use of such processes and makes them labour-consuming ones due to the large number of control measurements.

The thermal stability of Co silicide on single crystal and polycrystalline Si has been investigated. Co films were evaporated onto (100) Si and undoped polycrystalline Si and annealed in vacuum. Resulting silicide films were examined using Rutherford backscattering spectroscopy, scanning electron microscopy, electron-induced x-ray spectroscopy, and sheet resistivity measurements. We find that CoSi2 on single crystal (100) Si remains stable through 1000°C. In contact with undoped polycrystalline Si, intermixing begins at temperatures as low as 650°C for 30min annealing. The Co silicide and Si layers are intermixed after 750°C 30min annealing, giving islands of Si surrounded by silicide material, with both components extending from the surface down to the underlying oxide layer. The behavior of CoSi2 contrasts with results reported for TiSi2 which agglomerates on single crystal Si around 900°C but is stable on polycrystalline silicon as high as 800°C. Resistivity measurements show that the Co silicide remained interconnected despite massive incursion by Si into the silicide layer.

TiSi2 thin films were formed on crystalline and amorphous silicon substrates obtained by Ge+ and Ge++B+ implantation and optional subsequent annealing. Transmission electron microscopy, X-ray diffraction and electrical resistivity analysis revealed that the silicide formed on amorphous Si has more tendency to have a C54 structure rather than the metastable C49 structure. Also, the grain size is smaller and the silicide/silicon interface is smoother for silicides formed on amorphous Si. Comparison between implanted and unimplanted, (100) and (111) Si substrates indicated that the origin of the differences can be attributed to the latent energy stored in amorphous silicon, which favors the silicide with fine grains and promotes the transformation to the C54 phase. Non-random distribution of planar defects in C49 grains has been observed by plan-view TEM. A proposal that these defects are transformation stress induced microtwins is presented.

The geometrical shape and the thermal stability of the TiSi2/poly-Si interface on narrow lines has been studied. The examined line-widths varied between 0.8 μm and 1.5 μm. The thermal stability was found to strongly correlate to the actual line-width of the structures. At the onset of degradation, at and above 900°C, narrow lines were observed to disintegrate at a much faster rate than wider ones. Cross-sectional microscopy (TEM and SEM) revealed the TiSi2/poly-Si interface to be curved inwards. The interface bowing was found to be more pronounced on narrow lines. It is suggested that the interface bowing results from a mechanical pinning of the TiSi2/poly-Si interface by the side-wall spacers.

Titanium silicide (TiSix), used as polycide gate consists of TiSi1.1 and amorphous silicon (a-Si), was deposited by Plasma Enhanced Chemical Vapor Deposition method (PE-CVD). The effect of a-Si layer in PE-CVD Ti polycide gate dielectrics has been studied. In order to evaluate the a-Si layer effect, three types of samples were prepared on gate SiO2 film with following structures : a) a-Si / TiSi-1.1 / a-Si / phosphorus (P) doped poly-Si, b) a-Si / TiSi-1.1 / non-doped poly-Si / P doped poly-Si and c) a-Si / TiSi1.1 / P doped poly-Si, respectively. Furthermore, in order to avoid the influence of native oxide existence at the interface, the pre-cleaning treatment was performed in-situ on the poly-Si film surface before TiSi1.1 film deposition. The gate dielectric strengths of these samples indicate that the gate dielectric degradation in PE-CVD Ti polycide gate is greatly dependent on Si under layer crystallization. It is effective using a-Si film as the under layer in decreasing the gate dielectric degradation . This is due to the Ti oxide interlayer, formed at the interface of TiSi2.0 and poly-Si films, which restrains the TiSix local penetration.

The concept of using cobalt disilicide as a self-aligned metallization scheme for gate/interconnection and contact formation is gaining wide acceptance. The silicide formation on the gate will require a Co-metal film interaction with the underlying polysilicon that may be doped heavily. We have investigated the silicide formation kinetics during this reaction. The effect of different dopants (B,P, and As) and their concentration on the Co-Si interaction and the dopant redistribution during such reactions were investigated. The results from these studies will be presented and discussed.

The presence of a thin (10-30Å) oxide (“native oxide”) layer on a silicon surface prior to the deposition of another film on that surface can contribute to difficulties with subsequent device processing steps, e.g. contact metallization and high-temperature annealing or oxidation. Thus, the in situ process capability of “native oxide” removal affords an advantage over the conventional method of aqueous hydrofluoric acid cleaning prior to a film deposition step. This study describes such a technique, in which an in situ pre-deposition clean with C2F6 gas, using reactive ion etching (RIE) prior to tungsten silicide deposition, is employed. This technique allows post-silicide deposition high-temperature heat treatment and wet oxidation without loss of film adhesion or other obvious degradative effects. We also report the use of Secondary Ion Mass Spectrometry (SIMS) to show that this procedure has been effective in the removal of the oxide layer prior to silicide deposition. This study includes definition of the RIE etch parameters which provide acceptable etch selectivity of the oxide to silicon, and avoidance of excessive fluoropolymer formation on the silicon surface.

Rapid thermal annealed (RTA) bilayers of TiW/Ti were evaluated for contact metallization in advanced VLSI Si circuits. It was found that RTA and a minimum thickness of Ti are necessary to achieve consistently low p+ contact resistance. RTA has little effect on n+ and polysilicon contact resistances. With RTA, TiSi2 is formed at the Ti/Si interface and a thin nitrogen-containing layer is formed on the TiW surface. By controlling RTA temperature and time, the interaction between Si and TiW during RTA could be minimized while the gain factor of p-channel MOSFETs was not degraded. Moreover, the leakage currents of n+ and p+ contact chains did not increase after 30 minute anneals up to 525C

Controlled modifications in the electrical properties of metal/GaAs junctions were obtaind by a few different approaches. The first approach is based on modifications induced by solid state reactions occurring between the metal and GaAs substrate, resulting in compound formation and component redistribution. The characteristics of such contacts can further be modified when the contact metal is alloyed with another metal or with a dopant. The second approach is based on modifying the doping level of the near surface region of the GaAs. Here an enhancement of the barrier height was obtained by heavily counter doping the top GaAs region by recoil implantation of Mg from a Mg thin film irradiated by As− ions. The correlations between the electrical properties of the junctions and the physical processes taking place using the above mentioned approaches are discussed.

Low resistance Pt/Ti nonalloy contacts to GaAs, GaP, In As, InGaAs, and In Alas have been studied using Rutherford Backscattering. The samples were studied by comparing an as deposited structure to samples annealed at temperatures between 300°C and 600°C for 30 s. For all samples intermixing of the Pt and Ti was observed to start at 350°C. The Ti/HI-V semiconductor interface mixing was strongest for As when it was present, but In and Ga also strongly intermixed for anneals of 4S0°C and above.

Recently, thermally stable, low resistance In-based ohmic contacts to n-type GaAs have been developed in our laboratories by depositing a small amount of In with refractory metals in a conventional evaporator, followed by rapid thermal annealing. By correlating the interfacial microstructure to the electrical properties, InxGa1-xAs phases grown epitaxially on the GaAs were found to be essential for reduction of the contact resistance (Rc). This low resistance was believed to be due to separation of the high barrier (φb) at the metal/GaAs contact into two low barriers at the metal/InxGa1-xAs and InxGa1-xAs/GaAs interfaces. In this paper the effects of the In concentration (x) in the InxGa1-xAs phases and addition of dopants to the contact metal are presented. High In concentration is desirable to reduce the φb at the metal/InxGa1-xAs interface. Such contacts were prepared by sputter-depositing InAs with other contact elements, but the low Rc values were not obtained. The reason was explained to be due to an increase in the φb at the InxGa1-xAs/GaAs interface due to the formation of misfit dislocations. However, addition of a small amount of Si to the contact metals reduced significantly the Rc value. This contact demonstrated excellent thermal stability: no deterioration was observed at 400°C for more than 100 hrs. In addition, the use of this Ni(Si)InW contact metal allowed us to fabricate the low resistance ohmic contacts by one-step (simultaneous) annealing for “implant-activation” and “ohmic contact formation”, which simplifies significantly GaAs device fabrication process steps. For p-type ohmic contacts, low resistance contacts were fabricated by depositing the same NilnW contact material to p-type GaAs. This contact was also thermally stable during subsequent annealing at 400°C. Within our knowledge this is believed to be the first demonstration of low resistance, thermally stable ohmic contact fabrication using the same materials for both n and p-type GaAs.

Electrical, structural and diffusion characteristics of a solid phase reacted ohmic contact to n-GaAs are studied. Attempts were made to form a low band gap interfacial phase of InGaAs to reduce the barrier height at the conductor/semiconductor junction and thus yielding a low resistance, high reliablity contacts. The understanding of the interface is important from the point of view of device performance as well as device reliability. The contacts were fabricated by co-sputtering W, In and Te targets on n-GaAs with subsequent annealing. The as-deposited rectifying contacts became ohmic when annealed to 500°C, and showed a specific contact resistance of ∽5×10-6 ohm cm2. The Auger and Rutherford back scattering analysis of the interface revealed an InGaAs phase formation prior to the onset of ohmic conduction. The contacts were stable up to 500°C and the surface morphology was superior to presently used AuNiGe contacts. The contact pads were patterned by dry plasma etching without adversely affecting the GaAs substrate.

Mn–In–Co, Mn–In–Pt and Mn–Pt metallizations are used to form ohmic contact on Be-implanted rapid thermally annealed GaAs. The rapid thermal alloying of contact metallizations are performed in A.G. Associates Heat pulse system in nitrogen atmosphere in the temperature range of 350°C to 800°C for 5 seconds. The contacts were found to be ohmic at an annealing temperature of 450°C. The In–Mn–Co metallization showed higher minimum contact resistivity (5 × 10−4 ohm.cm2 ) than In–Mn–Pt metallization (1.5 × 10−5 ohm.cm2 ) for an annealing temperature of 700°C and time 5 seconds. The surface morphologies of In–Mn–Pt metallizations were smooth even after alloying at 700°C for 5 seconds. The Auger analysis shows outdiffusion of Ga and As into the contact metallization and negligible indiffusion of In and Mn into GaAs.

The oxidation of prereacted Pt films on (100)-oriented n-GaAs substrates was studied in the temperature range between 550 and 750°C using Auger electron spectroscopy and Xe+ ion profiling. The GaPt/PtAs2/GaAs structure formed during annealing in hydrogen was oxidized using a mixture of water vapor and hydrogen. The GaPt phase can be oxidized completely, whereas the inner PtAs2 and GaAs interfaces are left unoxidized. The oxidation of the platinum-gallium phase is self limited by the diffusion of the Ga through the gallium oxide overlayer. The oxide can be etched off to leave a structure consisting only of platinum-arsenide on the GaAs substrate.

The interactions between Ni and Ni/In/Ni thin-films and GaAs were studied by SEM, SAM and AES. The presence of a molten phase was observed for both contacts after annealing at 820°C for 3 minutes. This behavior was rationalized in terms of the presence of a ternary eutectic reaction in the gallium-nickel-arsenic system. DTA confirmed the existence of the reaction:

at 810°C. In the case of Ni/In/Ni, melting was thought to occur because of the segregation of indium metal to the contact surface and the subsequent melting of the nearly ternary interfacial region. Upon further cooling the formation of NiGa, NiAs, InxGa1−xAs and an unspecified compound Ni-In was believed to occur. The contact was shown to be either sintered or alloyed, depending upon processing conditions.

The formation of Pd-Ge layers was studied as a function of deposition and annealing using synchrotron Ultraviolet Photoemission Spectroscopy (UPS). Pd depositions ranging in thickness from 0.5 monolayers (ML) to 44 ML were examined in-situ on Ge (111) cleaved in ultra-high vacuum. The primary reaction components appear to be Pd2Ge and PdGe. Comparison of bulk and surface sensitive Ge 3d core levels for even the highest coverages indicates that Ge segregates to the surface at room temperature. Such low temperature segregation suggests that Ge can diffuse via a rapid diffusion mechanism.

We describe techniques of reliable metallization in InP-based systems for application to discrete and opto-electronic integrated circuits (OEIC’s). Strong metallurgical interaction between Au and InP-based compounds can cause serious contact degradation in light emitting diodes (LED’s). By analyzing this interaction in detail, an improved thin Au/Zn/Au p-contact technique has been developed. The results are compared with Pt/Ti contacts, and it has shown that both provide sufficient reliability under temperature and current stresses in LED’s. We then describe a metallization technique for flip-chip bonding of opto-electronic devices on other semiconductor chips for OEIC applications. An acceptable reaction barrier effect of Pt in AuSn/Pt/Ti metallization structure has been demonstrated and this structure has been used for a high-reliability, flip-chip integrated GalnAs/InP PIN photodiode/GaAs amplifier receiver circuit. We also discuss requirements for metallization for future monolithic OEIC’s by taking up an example of metal-semiconductor-metal photodiodes in InP-based systems.

Forward bias capacitance has been used to examine the Au/W/GaAs and Au/Pt/Ti/GaAs Schottky barriers present in power microwave MESFET devices to see if interface-state generation plays any role in the previously reported reverse bias barrier height aging process. If a constant carrier capture cross-section is assumed, forward bias capacitance has shown that for samples strongly susceptible to aging (i.e. the Au/W/GaAs samples in this study) interface-state generation is taking place during the aging process. The validity of the constant capture cross section assumption has been tested by examining the I-V properties. For those samples whose reverse I-V properties were not dominated by thermionic-field emission, similar increases in interface-state densities were evaluated from the I-V characteristics for the degraded samples.

The reliability of ohmic contacts to thin, heavily doped layers of GaAs is investigated. Pd/Ge/Au contacts to n-type GaAs display excellent electrical stability over extended periods of thermal stress. The contact resistance stays below 0.5Ω-mm during a 2500h, 280°C bake. Reactive ion beam assisted evaporation of Ti with N forms TiN which is introduced as a barrier layer in Pt/TiN/Ti/Au contacts to a thin p+ layer. The TiN layer allows greater process latitude in the sintering process and improves long term stability of the ohmic contact. The microstructure of the p-type contacts is examined with TEM and Auger profiling at different instances of the 2500h, 280°C bake and compared to the contact resistance measurements.

Several compositions of Al-Pt thin films have been co-evaporated on GaAs substrates to study the stability of the alloys at high-temperature anneals. The Al concentration in the alloys ranges from 45 at.% to 70 at.%, and we show that the films meet thermal stability requirements imposed by GaAs self-aligning gate technology for compositions between AlPt and Al2Pt.