Single crystal Al(111) films were grown on Si(111) surface at room temperature under a conventional vacuum condition using the partially ionized beam (PIB) deposition technique. The Al films were deposited with an ion to atom ratio of about 0.3% and an acceleration voltage of 1 kV. Transmission electron microscopy (TEM) analysis showed that the as-deposited films were single crystal with certain density of dislocation networks. These dislocations disappeared following a heat treatment at 450°C for 30 min. From X-ray diffraction and TEM patterns, it was observed that the Al(111) was aligned to the substrate with Al<1l0>//Si<1l0>. Possible mechanisms of the PIB epitaxial growth and a novel structural defect that is unique to this large lattice mismatch system are discussed.

In recent years extensive research has been conducted on growing heteroepitaxial layers of insulators, metals, and other semiconductors on silicon. This work promises to extend the use of Si (or, at least, Si substrates) far beyond present day devices into hybred semiconductor devices, optoelectronics, ballistic electron devices, and three-dimensional device structures. However, the “art” of heteroepitaxy is still poorly understood and much work remains to be done to realize most practical applications. Molecular beam epitaxy (MBE) represents an attractive technique for research and development of heteroepitaxy because of its relatively low growth temperatures, flexibility in working with different materials, and by providing a good environment for in-situ observation of the heteroepitaxial process. Using examples from recent heteroepitaxial work by molecular beam epitaxy in the areas of CaF2, NiSi2 and CoSi2, and GaAs on Si, this paper discusses how heteroepitaxial quality is affected by the relative surface free energies and strain (due to both lattice and thermal expansion coefficient mismatch). The goal is to produce better heteroepitaxial layers for device applications by an improved understanding of the process.

The use of the metalorganic chemical vapor deposition thin film materials technology in the heteroepitaxial growth of GaAs on Si substrates is of increasing interest for a wide variety of applications. This paper will describe the principles and applications of this materials technology and discuss possible future approaches to the growth of high-quality HI-V heteroepitaxial layers on Si substrates.

Tunneling images of vicinal Si(001) and Ge(001) cut with a tilt about [110] are presented. Si(001) samples cut with a 4· tilt exhibit double steps with many kinks and point defects, while 2· Ge(001) samples exhibit only monoatomic steps. The behavior of the steps is essentially described by a model due to Chadi. The procedure used to clean the surface can have a strong influence on the spacing of the steps.

The initial stages of heteroepitaxial growth of GaAs on Si have been observed using a technique of graded-thickness sample deposition. We find that an initial uniform passivating layer is grown, followed by three-dimensional nucleation determined by Ga diffusion and clustering, followed in turn by an interfacial reaction limited island growth mechanism. Results for various substrate temperatures and substrate orientations are consistent with the simple models of nucleation and growth.

The kinetics of desorption and scattering of Ga atoms on Si(100) surfaces are probed by laser-induced fluorescence detection of the gas phase species and by Auger analysis of the surface composition. The kinetic parameters are correlated with the structures deduced by LEED and the coverages determined by Auger spectroscopy. The binding energy of Ga on Si(100) is found to be a function of coverage, starting out at 2.9 eV at low coverages and decreasing to 2.3 eV for coverages between 0.5 and 1 monolayer (ML). Ordered growth is always observed for coverages below 1 ML, but above one monolayer the growth of islands occurs on the wellordered monolayer. The onset of island formation is a strong function of temperature. A model is proposed for the structures and energetics involved in the growth of Ga on Si(100). The results are discussed in terms of the implications for epitaxial growth of GaAs on Si.

Several surface treatment techniques have been used to study the effect of the Si surface on subsequent GaAs-on-Si epitaxy. In particular, the effect on the degree of island formation is addressed. Experiments have been carried out with GaAs film thicknesses in the range from one monolayer to around 50nm. Core level spectroscopy results for the monolayer films give information about the bonding character at the interface and suggest methods of improving the degree of two-dimensional growth. A particular Ga-prelayer technique is examined with high resolution TEM and found to give significantly different results than the standard MBE growth technique.

In the growth of thin films of compound semiconductors on (001) silicon substrates by vapor deposition techniques, it is usual to employ a two-step process. In this method, an initial (buffer) layer is first grown at a relatively low temperature; once a continuous film has formed on the substrate, its temperature is raised for the subsequent bulk growth. Carrying out the growth in a one-step process by heating the substrate to the final temperature before allowing the gases into the CVD reactor usually results in a polycrystalline aggregate. In this paper, classical nucleation and growth mechanisms are used to explain-the reasons for the different morphology of the one-step and two-step growth films.

The heteroepitaxial films on (001) silicon often contain a high density of stacking faults and twins. The occurrence of these planar defects is usually attributed to stresses that arise from lattice mismatch and/or thermal mismatch (differences in coefficients of thermal expansion) between the substrate and the epilayer. It is argued that, in fact, mismatch stresses play a minor role in the generation of planar defects. Instead, an alternative mechanism for their formation is proposed which is based on the facetted shape of nuclei and errors in stacking of {111} planes which occur during deposition on the facets.

Conventional and high resolution transmission electron microscopy have been used to investigate three systems grown by CVD or MOCVD: SiC/Si, GaAs/Si and GaP/Si. These systems have different lattice and thermal mismatches, and the results support the proposed model for the formation of defects.

In this work, a new model based on energy balance for heteroepitaxial growth on a patterned substrate and an additional thin buffer layer on top of it has been developed. The structure used in our model is assumed to be GeSi/buffer-Si/patterned-Si and comparisons are made with simple crystalline GeSi/Si. However, the model described here is quite general and can be adopted for any other material systems. Using this model, coupled with experimentally known material constants, the critical layer thickness (hc) of a lattice mismatched heterolayer can be determined for a patterned substrate, having a characteristic “seed pads” size (l), and a buffer layer thickness (hb). The dislocation-free condition under this case is also established.

The initial stage of the growth of GaAs on Si by, MOCVD, the reduction of the residual dislocations by annealing at high temperatures and the dependence of the growth temperature on the stress in the GaAs layer were studied. The density and the size of deposited GaAs islands at the initial stage of the growth in the two-step growth sequence strongly affected the domain property of the subsequently grown layer. For reducing the residual dislocations by annealing at high temperatures, to repeat the growth and the annealing was more effective method compared with the other annealing methods we tried. The stress in the GaAs layers showed a constant value independently of the growth temperature and the value was related to the thermal expansion between room temperature and about 350°C.

GaAs layers were grown on Si (001) substrates by molecular beam epitaxy (MBE) and migration enhanced epitaxy (MEE). They were examined by transmission electron microscopy, doublecrystal X-ray diffraction and Rutherford backscattering/channeling technique. Initial layer growth in both MEE and MBE was governed by three-dimensional nucleation but a stronger tendency for GaAs islands to align along the surface steps of Si was observed in the case of MEE. There was no measurable tilt between the (001) planes of GaAs and Si if growth was initiated by MEE at low temperature, prior to further growth by MBE at higher temperatures. On the contrary, the tilt angle was 0.34• when the entire structure was prepared by conventional two-step MBE. Rutherford backscattering measurements indicated a significant reduction in the density of defects throughout MEE/MBE GaAs in comparison with MBE GaAs.

GaAs layers were grown in recessed silicon trenches for monolithic integration of GaAs and silicon devices. These layers were examined using cathodoluminescence (CL) and transmission electron microscopy (TEM). The CL showed no dependence on distance from the sidewall edge within its limit of resolution. Cross-sectional TEM micrographs showed the GaAs grown on the sidewall to depend on the sidewall orientation. Material grown on the near-{111} sidewalls was comparable to that grown on the well bottom, while the GaAs grown on the near-{110} sidewalls showed poorer crystal quality. A photodetector was fabricated in the recessed GaAs/Si; this device could be easily adapted to a monolithically integrated structure.

The growth of GaAs on Si by MBE through openings in an oxide or nitride represents a convenient means for achieving monolithic GaAs/Si integration. We have examined a number of the materials growth and processing issues that must be resolved in order to achieve this goal. Some of the specific areas that have been investigated are (a) the effect of trench etching on the morphology of the patterned GaAs; (b) the dependence of patterned feature size on Hall mobility in both as-grown and postgrowth annealed samples; (c) the effect of annealing on the defect structure in the transition region from single crystal GaAs to polycrystalline growth; (d) the dependence of GaAs MESFET performance on proximity to the polycrystal transition; and (e) the performance of Si MOS devices following the GaAs MBE growth. Specific growth and processing issues concerning the integration of GaAs and Si device functions have also been examined.

We investigate two aspects of the initial stages of GaAs/Si growth: the effects of Si misorientation on GaAs island nucleation, and the structural changes occurring upon heating the buffer layer to the final deposition temperature. We observe that the GaAs islands tend to nucleate at Si surface steps and grow along them. The shape of the islands depends on the degree and direction of the Si misorientation from (100). Island coalescence occurs as the film grows, such that a 500Å film is almost completely continuous. In situ heating of a 30A film to 5750C for 15 minutes causes the islands to agglomerate, while similar treatment of the 500A film does not appear to expose more of the underlying substrate and in fact improves the film crystallinity.

The growth of high-quality single crystal GaAs on Si wafers up to six inches in diameter by organometallic chemical vapor deposition (OMCVD) is reported. These wafers have specular surfaces, excellent thickness uniformity, and are shown to have properties comparable to those of smaller diameter GaAs on Si wafers. The mechanical and electrical properties of the six inch GaAs on Si wafers are shown to be suitable for GaAs device fabrication.

Significant progress has been made in the OMVPE growth of GaAs directly on Si by the previously reported low-temperature growth technique. These films have been characterized by low-temperature PL, SIMS, TEM, and DLTS. The epitaxial layers, whose quality has been determined by PL measurements (4.2 K PL spectral width of heavy-hole exciton ≈ 3 meV), were implanted with 29Si+ for fabrication of MESFET channels. Background concentrations of ≈ 1014 cm−3 have been achieved for the first time after rapid thermal annealing without the need to use oxygen implantation or vanadium doping. SIMS measurements do not show Si pileup on the surface or much Si diffusion at the GaAs-Si interface, a significant improvement over earlier results. DLTS measurements and electrical characterization of the GaAs-Si heterojunction diode indicate the presence of only two trap levels (< 1014 cm−3 in concentration) in the GaAs ≥ 2.5 μm away from the interface.

Material properties of GaAs films grown on Si(321) substrates using molecular beam epitaxy (MBE) were evaluated and compared to films grown on Si(100) and Si(211). Dislocation densities in the GaAs(321) films, determined using transmission electron microscopy (TEM), were lower than those observed in GaAs(100) and GaAs(211), and the density of stacking faults in GaAs(321) also was quantitatively lower than in GaAs(211). Low-temperature (4.2 K) photoluminescence spectroscopy (PL) indicated that the tensile stress on the GaAs(321) films was greater than that on GaAs(100). These differences are attributed to changes in the strain-relaxation process caused by variations in the number of geometric arrangement of active-dislocation glide systems with different orientations. In addition, Si uptake near the GaAs/Si interface was less than 1/100 of a monolayer in GaAs(321) and 1/4 of a monolayer in GaAs(100). This difference is attributed to the presence of a non-polar (neutral) interface in the (321), whereas the (100) has a polar (charged) interface. MODFET devices with a I-)m gate length exhibited a transconductance of 180–200 ms/mm, comparable to devices on homoepitaxial GaAs(100).

The structural change of the thin low temperature (~450°C) deposited GaAs films and the role for conventional temperature growth were studied by RHEED and cross-sectional TEN observation. The formation of the threedimensional high quality single crystalline islands from continuous twin GaAs layer deposited at low temperature (~450°C) was clarified. These three-dimensional islands act as the seeds for conventional temperature growth.

The effectiveness of thermal annealing and strained layer superlattices (SLS's) in defect reduction in Si/GaAs structures was studied. The GaAs layers were grown on (100) Si substrates by low pressure MOCVD. They were evaluated by TEM, HREM, EBIC and PL. As-grown layers contained dislocation densities in the 108-109 cm−2 range, depending on the layer thickness. Post-growth and in situ annealing were performed on a wide variety of these structures. TEM examination showed that in situ annealing was more effective as it resulted in confining a large portion of the threading dislocations to the interface region. Furthermore, the interaction of threading dislocations to form closed loops was evident. Additionally, the effect of GaAs/GaInAs and GaInAs/GaAsP SLS's on dislocation bending was investigated. The former SLS, although not lattice matched to GaAs, proved more effective.

Abstract: Several different types of GaAs-AlGaAs heterostructures were grown on Si substrates by MOCVD. The defect density in as-grown samples (~108cm−2) was similar to that of GaAs layers grown directly on Si, and the crystalline quality of the material was observed to improve slightly with post-growth annealing at 900°C. We examined the diffusion of both Si and Zn dopants during this type of annealing and found only a small amount of redistribution of both species. Laser annealing of GaAs-on-Si was also examined as a method of reducing the defect density in the material - we observed substantial improvements in surface quality, but no change in sub-surface crystalline quality.