The National Technology Roadmap forecasts significant increases in performance for silicon devices over the next several years continuing the pace of the last 25 years. As the complexity and performance of the silicon have increased, so has the cost to manufacture the supporting packages. However, continued growth of the industry demands that package costs be held under control. A requirement of the Roadmap is a need for a significant lowering of cost over the period. On a per lead basis: for example, for cost/performance products in 1995 the range in per pin cost is 1.4–8 cents. These costs must move to 1–3 cents per lead over the next 15 years, while lead count increases from a few hundred to a few thousand. These costs will not be achievable unless we change how materials are developed and deployed to the market.

The loss of U.S. electronics market share during the last three decades is attributed to both the engineering education and the research emphasis away from manufacturing and systems. The engineering education in U.S., in spite of great progress during the last decade, is incomplete and fragmented and requires a comprehensive and system-level strategy.

The Materials Science and Engineering Laboratory at NIST has augmented its laboratory-based research in support of the U.S. commercial microelectronics industry by expanding its efforts in electronics packaging, interconnection and assembly (P/I/A) materials technologies. In conjunction with industry, university and other government agency partners, these new NIST efforts target materials technology issues that underlie the priorities contained within the various electronics industry technology roadmaps. A dominant aspect of the laboratory P/I/A program focuses on the in-situ metrology and data needs associated with the materials and complex material assemblies which comprise today's microelectronic components and circuits.

The expanding needs of mixed signal applications of thin film MCM technologies which combine analog, digital, power and opto-electric devices require a wide range of integral, thin film, passive components within the MCM structure. There is a need to incorporate these passive elements into the interconnect structure to reduce component count, decrease substrate area and to improve electrical performance. In this study, we investigated advanced material and processing technologies for the in situ formation of capacitor components during the fabrication of multilayer polymer/copper interconnect structures.

Amorphous BaTiO3 film having a dielectric constant of 10 to 40 depending on stoichiometry was deposited on a surface roughness controlled metallized polyimide surface at room temperature using the reactive partial ionized beam (RPIB) technique. Simple metal/insulator/metal(MIM) capacitors were fabricated and characterized. Hundreds of pF capacitance with <10−6 Amp leakage current were obtained depending on the top metal electrode size, dielectric thickness, and stoichiometry of dielectric film. Annealing treatment on dielectric film significantly enhanced the leakage current property. After thermal cycling treatment, it was proved that thin film integral capacitor was reliable enough to be used as a practical MCM application. Process defects control was necessary to improve capacitor yield.

The reliability of ceramic and plastic packages used in microelectronics is compromised by interface (delamination) and homogeneous (bulk) cracking that is initiated during processing and stress testing. These cracking failures have certain characteristics in that they begin at locations of geometric stress concentrations and propagate along typical failure paths. Characterization of these stress concentrations is therefore essential to a good design and for defining material response parameters such as bulk and interfacial fracture toughness. In this paper, applications of a general-purpose finite element technique for the characterization of stress concentrations are presented. The technique uses the full twodimensional elasticity solution for different materials that are bonded together. It is possible to use this technique to extract relevant material parameters, such as stress intensity factors, the J-integral, or energy release rate, and hence to eventually define the conditions necessary for crack initiation and propagation.

A constant depth scratch test (CDST) has been recently developed to quantify the shear strength of film-substrate interfaces. This test is capable of measuring interfacial adhesion as a function of position on the sample surface during a continuous scratch. Unlike many of the currently available tests which are applicable to a limited array of materials systems, or are experimentally complex, this test is quite versatile, and is relatively straightforward to conduct and interpret because of the constant depth geometry. The theoretical basis and the experimental set-up for the test have been previously presented. In this paper, extensions of the theoretical formulation to account for different debonding behaviors of different film-substrate systems are discussed. Experimental results generated with a number of systems, including chromium on glass, gold on aluminum nitride, gold on aluminum nitride with a chromium inter-layer, and polycrystalline diamond on aluminum nitride are presented.

In the present work, CuCr alloys with varying Cr content were sputter deposited on polyimide films, and the metal/polyimide thin films were maintained under 85° C/85%R.H. (T/H) conditions for the reliability measurements. Results showed that the peel strength without T/H treatments increased proportionally with the Cr content in the CuCr alloy layer(x) up to 17 at. %, and then saturated. Among the samples studied, the peel strength decreased with hold time under T/H conditions for all the cases, but most drastically for the sample with x=8.5. The very poor peel strength of that sample (x=8.5) was attributed to the occurrence of interfacial failures which were thought to take place along Cr-oxide/polyimide interfaces.

Chip-on-Board technology (COB), or the currently more often used MCM-L acronym (MultiChip Module - Laminate), has long been touted as the low cost, high density electronics packaging choice of the future. Unfortunately, poor reliability performance in comparison to traditional plastic packaging, has been a trademark of COB/MCM-L. Recent advances in processes and materials for COB/MCM-L are providing a paradigm shift in reliability, and providing cost effective high reliability packaging solutions for COB/MCM-L. This paper examines the history of recent advances in liquid encapsulated COB/MCM-L and provides guidelines for selecting appropriate materials and processes for their successful implementation into cost effective manufacturing.

One of the most important subjects for semiconductor packages is preventing cracks which occur when the entire package is exposed to a soldering temperature of 215 to 260°C in the surface mounting technology. Cracking, as seen during temperature cycling tests is also a problem to be addressed. This paper reports the design of epoxy encapsulating compounds for highly reliable semiconductor devices which require the following properties: (1) toughness of matrix resin, (2) low moisture absorption, (3) high adhesion to insertions, and (4) reduction of thermal stress. The moisture absorption was lowered and the toughness was improved by using hydrophobic epoxy resins and high filler loading. The latter reduced the thermal stress, and it was effective for lowering the moisture absorption and increasing the fracture toughness of molding compounds. The reliability tests results were also considered in terms of physical properties of molding compounds.

Making the transition from mechanical testing of mold compounds to actual Integrated Circuit (IC) plastic package reliability requires an understanding of material behavior under the influences of moisture, temperature, and varying load conditions. This paper will focus on the role of material strengths, strain energy, and nonlinear effects in determining plastic package reliability. Examples of correlation between materials testing and reliability data will be presented.

A modem VLSI device is a complicated three-dimensional structure that consists of multilayer metallization conductor lines which are separated with interlayer-dielectrics as insulation. This VLSI technology drives the IC device into sub-micron feature size that operates at ultra-fast speed (in excess of > 100 MHz). Passivation and interlayer dielectric materials are critical to the device performance due to the conductor signal propagation delay of the high dielectric constant of the material. Low dielectric constant materials are the preferred choice of materials for this reasons. These materials, such as Teflon® and siloxanes (silicones), are desirable because of their low dielectric constant (∈1) = 2.0, 2.7, respectively. This paper describes the use of a low dielectric constant siloxane polymer (silicone) as IC devices passivation layer material, its chemistry, material processes and reliability testing.

This paper describes the viscoelastic characterization of a highly filled epoxy molding compound commonly used in electronic packaging applications. Both stress relaxation tests and constant strain rate tensile tests were conducted. The material was found to be nonlinear in its viscoelastic behavior and to be amenable to horizontal shifting to form master curves. A representation of the master stress relaxation curves in terms of a Prony series is given, and the use of this representation illustrated in the context of both linear and nonlinear representations of the viscoelastic behavior to predict the results of the constant strain rate experiments.

Stresses in thin polymer films have been studied for some time by using wafer bowing, bending beams, microstructure release, and laser holographic techniques. An alternative technique for measuring stresses in thin films is discussed in the following paper. Piezoresistive anisotropically etched single crystal silicon pressure sensors are sensitive not only to applied pressure, but also to applied package stress. Deposited passivation materials, like silicone gels and polyimides, have been observed to change the sensitivity of the pressure sensor. In the current work, a thin, conformal polymeric coating (parylene C) is being developed for these pressure sensors. This thin film has been observed to reduce the sensitivity of the device as a function of the film thickness and modulus and the silicon thickness and modulus. The parylene C thin films exhibit a consistent change in film stress during annealing indicating a modification to polymer crystallinity and a corresponding change in material properties. Qualitatively, the electrical output on the pressure sensor compares favorably with measurements taken using wafer bowing. Experimental DMA and TMA work has been performed to determine the modulus (7.84 × 105 psi) and CTE (39 ppm/°C at 25 °C) of the material. However, literature values of modulus (4.1 × 105 psi) have been used with finite element analysis to model the stress effect more accurately for the thin conformal coating on the pressure sensor device. These results indicate that the sensitivity of the pressure sensor will be reduced approximately quadratically as a function of the polymer coating thickness. An empirical function has been derived to estimate sensitivity loss as a function of substrate (i.e., initial diaphragm material) modulus and thickness and coating modulus and thickness.

Adhesive failure of rigid-flex printed circuit boards (RF-PCBs) during use has degraded the performance of military avionics systems. Adhesive failure is often caused by differences in the coefficient of thermal expansion (CTE) between the materials used in RF-PCBs and by moisture absorption by the adhesives and polyimide (PI) films. High-performance thermoplastics were investigated to replace the epoxies, PIs, and adhesives currently used in RF-PCBs. Because thermoplastic materials are remeltable, adhesive bonding may be replaced by fusion bonding to join RF-PCBs. Fusion bonding would eliminate problems with material compatibility and differences in the CTE encountered with adhesive bonding. Industries that would benefit from this research are manufacturers of aerospace instrumentation, medical equipment, automotive systems, computers, telecommunications equipment, industrial instrumentation and controls, and consumer products, such as stereo systems and calculators.

An extensive survey of high-performance-engineering thermoplastic materials was performed, and samples of the more promising materials (both films and chopped fiber reinforced) were obtained for preliminary screening tests. The tests performed were chemical resistance, water absorption, tensile strength, flexibility, and solder resistance of bare dielectric. From these tests, a glass-filled liquid crystal polymer film made by Hoescht Celanese Performance Films best met the performance criteria compared with the thermoplastics tested.

Microstructural differences in copper deposited by four techniques commonly used in the microelectronics industry were previously reported. Grain size, preferred orientation, and near surface chemistry were considered. [1] Prediction of the reaction rates were made based on these differences and then correlated with actual measurements. [2] In aerobic conditions the grain size dictated the reaction rate, the smaller the size the faster the rate.[3] The composition of the surface film formed during etching was examined. The trends in chemical concentrations on the surface film vary for each sample, but the relative constituent amounts correlate to the grain size of the original copper samples. Thus, there is further evidence that during exposure to aqueous solutions of cupric chloride, copper corrosion, in terms of both etch rate and film composition, is dictated by grain size of the original copper and not other microstructural factors.

It is known that aluminum will readily form aluminum hydroxide during aqueous exposures. Thick oxide layers with a typical pseudoboehmite (fibre-like network) structure and bayerite crystals were observed on the aluminum metallization after the aqueous cleaning process. The study investigated the effect of a deionized (DI) water cleaning process (recently implemented to replace CFC-based cleaning technology) on the surface chemistry and corrosion behaviour of aluminum wire bond pads. The study also correlated the wire bond yield and oxide thickness with various water cleaning process parameters. The wire bond yield and reliability issues are discussed briefly.

Aluminum-matrix composites are attractive in their combination of low CTE and high thermal conductivity. Anodizing is an effective surface treatment for improving the corrosion resistance of aluminum-matrix composites. ForSiC filled aluminum, anodizing was performed successfully in an acid electrolyte, as usual. However, for AIN filled aluminum, anodizing needed to be performed in an alkaline (NaOH) electrolyte instead of an acid electrolyte, because NaOH reduced the reaction between AIN and water, whereas an acid enhanced this reaction. The concentration of NaOH in the electrolyte was critical; too high a concentration of NaOH caused the dissolution of the anodizing product (A12O3) by the NaOH, whereas too low a concentration of NaOH did not provide enough ions for the electrochemical process.

Nickel filaments of 0.4 μm diameter gave polyethersulfone-matrix composites with high electromagnetic interference shielding effectiveness and low surface impedance at 1–2 GHz. With 7 vol.% nickel filaments, the composite exhibited shielding effectiveness 87 dB (compared to 90 dB for solid copper), surface impedance 1.2 Ω (same as for solid copper), tensile strength 52 MPa, modulus 5 GPa, ductility 1.0% and density 1.87 g/cm3. The low surface impedance is valuable for microwave waveguides.

The addition of a second discontinuous filler (silica fume) that is essentially nonconducting to a composite with a comparably non-conducting matrix (cement) and a conducting discontinuous filler (carbon fibers) was found to increase the electrical conductivity of the composite when the conducting filler volume fraction was less than 3.2%. The maximum conducting filler volume fraction for the second filler to be effective was only 0.5% when the second filler was sand, which was much coarser than silica fume. The improved conductivity due to the presence of the second filler is due to the improved dispersion of the conducting filler. The silica fume addition did not affect the percolation threshold, but the sand addition increased the threshold.

High thermal conductivity heat sinks for thermal management in electronic packaging is enabling to a variety of advanced electronic applications. Heat sinks in industrial semiconductor application have thermal conductivities generally less than 180 W/mK, and frequently have large expansion mismatch with chips such as silicon and gallium arsenide. A unique technology of producing graphite fiber reinforced copper (Cf/Cu) composite has been developed that produced thermal conductivities up to 454 W/mK utilizing a K=640 W/mK fiber reinforcement (with a potential for 800 W/mK when utilizing a K = 1100 W/mK P130 fiber) and thermal expansion that can be matched to chip materials. The process consists of utilizing a hollow cathode sputtering process to deposit a bonding layer followed by copper on spread graphite fibers, which are then consolidated into composites with architectures to achieve desired thermal conductivity and thermal expansion. The copper thickness determines graphite fiber loading up to 80 %. In heat sink applications, where the electrical conductivity of the graphite fiber reinforced copper composite is a problem, processing has been developed for applying electrically insulating diamond film, which has high thermal conductivity and acts as a heat spreader.