Throughout the past four decades, both the productivity and performance of microelectronics technology have advanced at exponential rates. In reality, exponential advances do not continue endlessly. Consequently, the purpose of this discussion is a systematic assessment of early XXI century opportunities for multi-billion transistor chips or gigascale integration (GSI).

An Interconnect Architecture Optimization (IAO) methodology is proposed. The algorithm makes use of fundamental RLCLL2 relations for wiring delays, as well as predictive 3D interconnect density function histograms with y and x axes of wire length and inverse gate delay. The fundamental RLCLL2 relations determine “maximum” wire lengths as a function of wiring size within the wiring hierarchy; the 3D histogram establishes the pre-physical design allocations of wiring nets within the hierarchy. The decision process begins with the set-asides of wiring for power, clock, and vias, and ends with an optimized number of wiring levels and sizes. Some of the major conclusions of the preliminary analyses are: there are no significant problems with wiring at the lowest level as long as the local wire lengths are appropriately scaled; the MOSFET device may not be able to provide enough current to satisfy the capacitive fanout loads within the future allocations of clock period; and the global wires, despite significant improvements in performance, will continue to provide a design and technology challenge for larger chips and higher frequencies.

The performance and cost of the logic ICs is more and more dominated by the interconnections. Reducing the capacitances in the advanced processes, especially with low k dielectrics, is a priority, while a differentiated approach can be applied for lowering the connection resistances, e.g. in adapting the interconnect material to specific levels. Integrating new materials leads to difficult trade-offs in order to achieve a good electrical performance of the circuit. Finally the increased number of levels of interconnection addresses other fields like integration density, defectivity reduction or cost.

Recently IBM announced the first implementation of full copper ULSI wiring in a CMOS technology, to be manufactured on its high-performance 0.22 um CMOS products this year. Features of this technology will be presented, as well as functional verification on CMOS chips. To reach this level, extensive yield, reliability, and stress testing had to be done on test and product-like chips, including those packaged into product modules. Data will be presented fom all aspects of this testing, ranging from experiments designed to promote Cu contamination of the MOS devices, to temperature/humidity/bias stressing of assembled functional modules. The results in all areas are shown to be equal to or better than standards set by our current AI(Cu)/Wstud technology. This demonstrates that the potential problems associated with copper wiring that have long been discussed can be overcome.

We report the integration of six levels of Cu interconnects using dual inlaid patterning in a 0.2 μm logic technology. A review of process technology as well as device performance shortcomings using conventional aluminum metallization has been presented. Two tantalum based barriers, TaNx and Ta-Si-N as well as a titanium based barrier, CVD TiN, have been evaluated for their applicability. The use of embedded barriers wherein the barrier is formed below the surface of the dielectric has also been discussed as a potential option. No degradation to the device front-end parametrics were found with the choice of an appropriate barrier. Planarization by Cu CMP introduces surface topography that needs to be minimized in order to process multiple levels of interconnects within specified sheet resistance distributions for a range of line widths. Excellent results with highly planarized levels of metallization have consistently been achieved through an optimization of the unit processes and device integration.

Interconnect delay is believed to have a dominating impact on the speed of large logic circuits (such as micro-processors) when the Si technology is scaled into sub- 0.25um generations. In this paper, we analyzed interconnect scaling issues based on leading micro-processor trend data, simple RC delay model and the “Rents' rule”. It was concluded that, in order to not limit the speed of large logic circuits, “fat” metal wires need to be used for upper metal layers, which will lead to a rapid increase of required number of metal layers (>10) for sub-0.25um technology generations. Introducing Cu and low ε interconnect system can delay this rapid increase by ∼1 generation. Creating multiple clock frequencies in large logic chips and reducing the size of high frequency islands appears effective in containing the interconnection delay problem. Therefore, the proposed interconnection scaling/development strategy is to introduce Cu and low ε dielectric into manufacturing in next 1∼3 generation (0.25um∼0.13um), develop low cost and high yield interconnect system to enable ∼10 interconnect layers, and improve circuit design methodology to reduce high frequency island size.

Ionized Metal Plasma (IMP) technology has been developed for liners and wetting layer deposition of sub-quarter-micron devices. Numerical modeling showed the unique advantages of IMP source over ECR source and long throw sputtering in enhancing bottom coverage. Ti and TiN bottom coverage up to 70% were demonstrated on 0.18μm contact holes. The deposition rate, uniformity, bottom coverage and film stress were optimized by tuning RF and DC powers, process pressure and bias power. In situ TiSi2 were formed in high aspect ratio contacts by depositing IMP Ti at an elevated temperature. The precisely controlled microstructure of IMP TiN film enabled low temperature aluminum planarization. The extendibility to 0.13μm technology node was demonstrated, and the application in copper metallization was revealed.

The integration of Cu interconnections will require sophisticated structures to prevent Cu from coming into contact with devices. The barriers for Cu also must have good adhesion with dielectric and Cu, and yield desirable microstructure of Cu. This paper discusses several critical barrier requirements and compares the properties of Ta and Ti/TiN barrier systems.

We review progress on growth of direct-bandgap GaInP/GaP and other materials for light emitters monolithic on silicon, and discuss design, fabrication, process compatibility, and performance issues for optical emitters and detectors made in these materials.

Texture control of Al and Cu by underlying refractory metal is discussed. Al texture can be controlled with underlayer metals like as Ti and TiN which have the same atomic arrangement within 3% misfits to Al. Cu texture can be also controlled by underlayer TiN in spite of a large difference in inter-atomic distance of Cu and TiN. Since the epitaxial growth of TiN on Cu is observed, it is suggested that epitaxial growth may occur at the early stage of Cu deposition on TiN.

The electromigration performance was evaluated in double level interconnects with W-stud via. It is confirmed that highly <111> textured Al and Cu have high electromigration resistance. Both the diffusion of Cu in Al-Cu and Al drift are suppressed in <111> textured Al-alloy interconnects, and Cu drift is also suppressed in Cu damascene lines formed on <111> textured TiN. Grain boundary diffusion and the interfacial diffusion would be suppressed in highly textured metals with underlayer and it is speculated that interfacial diffusion is more important in Cu damascene lines.

As the device dimension decreases, the number of metal layers increases and the metal pitch decreases, Al dual damascene has been known to achieve low fabrication cost because the fabrication processes can be simplified by using Al sputter-filling technology and Al CMP. However, from the electrical characteristics and reliability point of view, it was not clear if the Al dual damascene is suitable for fine pitch metallization. In this paper, we compare via characteristics among W-plug, Al-plug and Al dual damascene for multilevel interconnects.

We investigated the via resistance and electomigration characteristics. Al dual damascene was formed by Al hot sputtering to fill via and trench, and by subsequent Al-CMP. The electromigration lifetime for via holes with misalignment between the 1st and 2nd Al for dual damascene is larger than that for conventional Al plug. On the dual damascene structure, via holes are opened first, then 2nd metal trench are patterned. Even misalignment between the 1st via and the 2nd Al occurs, contact area for dual damascene become large because of making contact at both of the via top and the side wall of the 2nd Al. The electromigration lifetime is longer for dual damascene with misalignment, in compared with that for Al plug and W plug with misalignment. Via resistance for dual damascene is almost the same as the via resistance for Al plug, which is lower than W plug. Via yield for dual damascene with misalignment is better than that for Al plug and W plug.

In conclusion, we compared W-plug, A plug and Al dual damascene for multilevel interconnects. Al dual damascene was found to be durable and reliable in structure and process against misalignment in terms of electromigtration lifetime and via resistance, as well as yield. Al dual damascene is the most promising technology for fine-pitch metallization.

Interconnection metallization uses film stacks, often composed of thin (<10 nm) Ti, TiN, or Ti/TiN underlayer(s) with a thick (200–1000 nm) Al-alloy film deposited on top. The texture or preferred orientation in such film stacks has important implications for both processing and reliability. Earlier studies' have demonstrated the importance of the underlayers on Al texture; however, to date no systematic work has been done on the effect of processing conditions on underlayer texture. This study examines the effect of deposition parameters on the underlayer texture development as well as the effect of this underlayer texture on subsequently deposited Al-alloy films. Fiber plots were obtained for Ti <002> and <101> and Al <111> reflections for a series of 20 nm Ti/ 10 nm TiN/400 nm AlCu films using both a conventional Siemens D500 diffractometer with a pole figure attachment and a Siemens HI-STAR Area Detector system using Cu radiation from a rotating anode source. Because of overlap between the Al <111> and Ti <101> reflections, the Al was removed with a subtractive etch. In this way both the Al and underlayer film textures could be quantified. It was found that the Ti and Al-alloy film textures vary depending on the deposition temperature, deposition method and final film thickness. For example, an increase in the substrate temperature from 300° to 500°C caused the Ti film texture to change from <002> to <101>. Additionally, switching the TiN deposition process from physical vapor deposition (PVD) sputtering to chemical vapor deposition (CVD) in a Ti/TiN/AlCu film stack caused a degradation in the AlCu <111 > texture.

Thin Al films alloyed with three different compositions (0.1%, 1%, 5% by weight) of Yttrium were deposited by D.C. Magnetron Sputtering onto oxidized Si wafer substrates. The samples were furnace annealed at 425 °C for 30 minutes. Resistivity measured for the as-deposited and annealed Al(0. lwt% Y) were 3.07 and 2.57+/−0.25 μΩcm respectively. Al(0. lwt% Y) was also annealed by furnace annealing (FA), rapid thermal annealing (RTA) and rapid photothermal annealing (RPA). RPA gave a residual resistivity of 2.67μΩcm in 5 minutes and at a temperature of 350 C for Al(0. lwt% Y). Mean time to failure for AI(0. lwt% Y) samples at a current density of 3.2+/−0.5×106A/cm2 at 30 C was 50 hours. TEM results showed grain size variation from 0.5 to 2 μm.

Diffusion-induced failures such as stress-induced voiding and electromigration (EM) are a major concern for interconnect metallization in silicon integrated circuits. The addition of solute elements to aluminum interconnects often leads to “blocking” of high diffusivity paths such as grain boundaries and thus to an improvement in the resistance to electromigration failure. This research investigates Al-In, Al-La, and Al-In-La alloys to improve interconnect EM resistance. The choice of these alloying elements is based on the fact that they have negligible solid solubility in aluminum and are homovalent. Lower solubilities may lead to grain boundary stuffing and hence to improved EM resistance. In addition, the homovalency minimizes the adverse effect on the metal resistivity from addition of impurities to aluminum. Multicomponent diffusion principles are used to tailor aluminum-based ternary alloy compositions which would exhibit the multicomponent effect of zero flux planes (ZFPs), or regions in the reaction zone of a diffusion couple where the flux of a component goes to zero. This study involves modeling the occurrence of ZFPs for aluminum in several diffusion couples of Al-In-La, thus limiting the bulk diffusive spreading of aluminum so that the electromigration behavior can be inhibited or eliminated. This paper presents our experimental findings and discusses the modeling approach to determine ternary alloys exhibiting ZFPs.

We discuss simulators of the deposition of metal films onto substrates containing vias and trenches. Our Monte Carlo simulations of Al are based on extensive first-principles and molecular dynamics (MD) data for atomic-level energetics and transport rates. We find that surface mobilities are highly anisotropic, and that this has a pronounced influence on film morphology. We have investigated the effects of faceting and grain boundary grooving on step coverage, together with the variation of morphology with deposition rate, temperature, and length scale. Mass transport across low index facets is extremely slow near equilibrium, and this can inhibit the smoothening of surfaces and the elimination of depressions during annealing. The MC model also predicts grain structures during polycrystalline film formation, and the generation of preferred crystallographic orientations (texture). We present MC simulations for a range of conditions, and provide comparisons with experiments on the sputter deposition of Al and TiN films. Results from the MC model are being incorporated into a continuum model based on level-set methods, and we expect that this will form the basis for a simulator that can efficiently explore a wide range of conditions.

Results from a statistically designed experiment studying the effects of initial substrate temperature (A), precursor pulse time (B), diluent gas flow rate (C), and their interactions on film properties of programmed rate chemical vapor deposited aluminum are presented. Deposition rate, reflectivity, absolute and normalized roughness, and grain orientation were the response variables investigated. A two level, three factor (23) full factorial experimental design was used. Five center cell replicates were used to estimate cell standard deviations. The experiments were conducted using tri-isobutyl aluminum (TIBA) as the precursor in a lowpressure chemical vapor deposition (LPCVD) cold wall reactor. Effects were considered significant at the 95% confidence level. Initial substrate temperature (A) affected deposition rate and reflectivity. Diluent gas flow rate (C) affected deposition rate, normalized roughness and film texture. The precursor pulse time/diluent gas flow rate interaction (BC) affected film reflectivity and absolute surface roughness, while the initial substrate temperature/diluent gas flow rate interaction (AC) affected film texture.

A new atomistic scheme for simulating polycrystalline thin film deposition based on a Monte Carlo approach has been developed. Simulations of polycrystalline aluminum deposition and annealing at different temperatures are presented. The time evolution of the film morphology for those temperatures is discussed. During deposition, columnar growth is observed at low temperatures. Grain growth takes place mainly during annealing. Faceting and selection of preferred crystal orientations (texture) is observed.

Mg is one of the elements that are regarded as having a beneficial effect on the Al electromigration (EM) lifetime. In this paper, we compare the EM behavior of 0.4 μm wide passivated Al-1%Mg-0.5%Cu, Al-0.5%Cu and Al-l%Si-0.5%Cu lines. Plan-view transmission electron microscopy and focused ion beam imaging reveal that Al(MgCu) film undergoes bimodal grain growth. Auger electron spectroscopy and secondary ion mass spectrometry show a strong surface segregation and a severe bulk depletion of Mg. Additionally the line-width dependence of the rate of the resistivity decay during aging shows also a different behavior for Al(MgCu) compared to Al(Cu) and Al(SiCu). All these findings are consistent with the EM results that Al(MgCu), processed with our experimental conditions, has both the lowest median time to failure and deviation in time to failure. The results are discussed in the light of the effect of Mg addition on the microstructure and of the great surface activity of Mg.

A non-destructive, non-contact method is described for imaging resistance variations along electrical conductors such as interconnects. In its basic implementation, an intensity modulated laser beam is scanned over the circuit carrying a d.c. current and the voltage induced in the circuit at the modulation frequency is used to vary the intensity of a synchronously scanned display. Resistance variations, such as caused by defects, produce variations in the image thereby identifying their spatial location. The voltage signal depends on a number of parameters including the temperature coefficient of resistivity of the conductor, the power of the incident laser, the absorption coefficient of the conductor and the rate of thermal diffusion to the surroundings. One advantage of the method is that it is possible to produce images of conductors below the surface. Whilst there is a degradation in contrast when imaging sub-surface features, it is still possible to identify and distinguish, for instance, tungsten vias and aluminum interconnects passivated by several microns of dielectric, as well as electromigration-induced damage. Under certain circumstances, other features in the immediate vicinity of the conductors, such as remanent photoresist and decohered interfaces, can also be imaged.

The reliability of microelectronic devices containing multilayer structures is profoundly influenced by the interfacial strength (adhesion) and resistance to fracture (debonding) of the many resulting bimaterial interfaces. Adhesion and consequent structural integrity are closely related to composition and processing conditions which determine key interfacial parameters, such as interfacial impurities, morphology and adjoining microstructures. Residual stresses, thermo-mechanical cycling and mechanical loading may drive time dependent fracture in these multilayer interconnect structures. Moisture present in the atmosphere and perhaps moisture present in the layers themselves can lead to premature failure and reduced lifetimes of these devices. We present unique data showing the effects of interface non-planarity on the interface fracture energy and the time-dependent delamination processes. Data is presented showing the effects of the phase angle of loading on the interface fracture energy and subcritical debonding processes. Behavior is rationalized in terms of the salient chemical reaction rate occurring at the debond tip. Implications for life prediction of devices are discussed.