Low resistance ohmic contacts for silicon devices commonly incorporate silicide materials as part of the contact. The electrical characterisation of ohmic contacts requires the use of various test structures such as the Cross Kelvin Resistor in order to determine the specific contact resistance ρc. This paper describes the results of using a three-dimensional finite element model of a Kelvin Resistor test structure in order to determine the influence of the electrical and geometrical parameters of a silicide-well on the magnitude of ρc. The same model of the test structure is further used to model the current density in the contact region. The results indicate that the presence of a silicide-well leads to reduced values of both ρc and the current density.

Profile evolution simulations during chemical vapor deposition based on a 2-D continuum model reveal that the type of surface kinetics plays an important role as a measure of determining step coverage of films deposited in a high aspect ratio trench or via. The linear surface kinetics, resulting from adsorption rate limitation, is found to be difficult to bring about conformal step coverage in a deep narrow trench without reducing the growth rate considerably; that is, under such a condition void free filling can not be achievable with holding an appropriate growth rate. High tendency of the precursor for chemical equilibrium on a surface, tending to cause the non-linear surface kinetics by surface reaction limitation, is mainly responsible for the significant improvement of step coverage in TEOS-based depositions.

The effect of capping layer (Ti vs TiN) on CoSi formation and CoSi2 sheet resistance has been investigated. Resistance measurements and XTEM analysis have been used to show that the Ti cap lowers the activation energy for CoSi formation by gettering the O2 from the RTA (rapid thermal anneal) ambient and eliminating the formation of SiO2 between the growing CoSi and the Co. The sheet resistance of cobalt silicide formed from Co/Ti and Co/TiN bilayers on poly- Si lines was measured as a function of linewidth and RTA temperature. With a Ti cap, the sheet resistance is low and independent of temperature, and the RTA process window is large.

The thermal stability of patterned cobalt silicide layers grown on amorphous silicon has been studied in the temperature range between 850 and 1000 °C. The degradation of patterned CoSi2, detected by resistance measurements, occurs via grain agglomeration at a temperature ∼100 °C lower than in blanket film. The reduction of the stability window in patterned samples is due to geometric constraints,. which results in a greater growth rate of the median grains with respect to lateral grains.

MicroRaman measurements on titanium silicide films grown on single-crystal and polycrystalline silicon substrates doped with As, BF2 and P have been performed. The data collected on patterns of different areas and shapes, but comparable doping level show that the doping has negligible effects both on C54 nucleation center density and on activation energy for the C49/C54 phase transition. On the contrary, substrate strongly affects the C54 growth rate, ruling the ability of the C54 phase to propagate after the nucleation.

We propose a methodology for systematic reactor design and optimization of operating conditions. The reactor can be designed systematically through the following steps: extraction of the chemistry from small-scale experiments, simulations for the virtual large-sized reactor configurations using the chemistry obtained from small-scale experiments, and final optimization by actual experiments on the real reactor manufactured according to the results of the simulation experiments. We call this technique ECONOMIX (Experiment, COmputer, kNOwledge MIXed CVD Process Design). The validity of this theoretical approach was confirmed for the WSix CVD process. The chemistry of the WSix CVD process was obtained from the tubular hot wall reactor. The rate constants of consecutive reaction were re-determined using two-dimensional simulation with consideration of temperature distribution. The growth rate and composition ratio were simulated for the cold wall reactor using reaction kinetics obtained by tubular hot wall reactor analysis. The predicted growth rates and composition ratios of Si/W showed good agreement with the experimental data. Therefore, the theoretical approach, ECONOMIX, is valid for the design of CVD reactor. We can design reactors and optimize operating conditions efficiently by this theoretical approach using computer simulation coupled with small-scale experiments.

As the interconnect RC delay plays an increasingly dominant role in the performance of deep submicron ULSI devices, Cu and low-k dielectric materials are deemed necessary to replace the traditional Al and SiO2 system to lower both the resistance and capacitance of metallization. This paper presents a systematic simulation method to assess the impact of Cu and low-k dielectric to the system speed and cross-talk noise for 0.18-μm design rules (0.6 μm pitch), and determine the practical process windows for metal line aspect ratio and the structural configuration of dielectrics. It was found that the high performance requirements for 0.18-μm devices (600 MHz and cross-talk <0.3 on a 2×2 cm2 chip) cannot be met by simply replacing Al with Cu or SiO2 with low-k dielectric (k=3), without any change in the interconnect architecture. By reverse scaling the metal pitch to 2× at upper levels, on the other hand, one can easily find a manufacturable process window, even with the Al and SiO2 system. Case studies on R and C of various structural configurations and boundary conditions have been performed, including Cu barrier layer thickness, metal gap fill and capping layer thickness of low-k dielectrics, as well as the influence of the lower and upper metal plates. The significance of the results on the strategy of implementing Cu/low-k interconnects versus extending Al/SiO2 will be discussed.

We have deposited TiN films by using ion-beam-induced chemical-vapor-deposition (IBICVD). Tetrakis-dimethyl-amido-titanium (TDMAT) was used as a precursor. N2 and Ar gas were used to generate the plasma and the ions in the plasma were extracted by using two electrically isolated grids. The energy of ion beam was about 115–127 eV. The use of N-ion beam significantly lowers the resistivity and carbon content of TiN film (∼320 μΩ-cm, 15 at.%), compared with the thermally decomposed film (∼6000 μΩ-cm, 36 at.%). The use of Ar ion beam also considerably lowers the resistivity of films (∼800 μΩ-cm), but does not reduce the carbon content. The step coverage of the thermally-decomposed film was about 70 %, while the step coverages of the films deposited using N2 and Ar ion beams were about 0 and 30 %, respectively, in 0.5 μm x 1.5 μm contacts. The etch-pit test showed that 50-nm-thick films deposited by using N2 and Ar ion beams prevent the diffusion of Cu into the Si substrate up to annealings at 550 °C and 600 °C for 1 hour, while the thermally decomposed film fails at 500 °C.

TiN film is applied as a diffusion barrier and an adhesion promotion layer in the ultralarge scale integrated circuit (ULSI) devices. These TiN thin films are usually deposited by sputtering and chemical vapor deposition (CVD) methods. The CVD method is now studied intensively due to its satisfiable step coverage and compatibility with current device fabrication process. There are several different CVD methods already proposed such as LPCVD, MOCVD and PECVD. These proposed CVD methods have many disadvantages such as impurity incorporation and particle generation due to gas phase reactions between source and reactant gases. To solve these problems, we propose a new CVD method to reduce impurities and particles which is the pulsed source chemical vapor deposition (PS-CVD) method. In this method, the source, reactant and purge gases are introduced into reaction chamber, separately. TiN films are deposited using TiCl4, NH3 and Ar by alternately introducing into reaction chamber. In detail, TiCl4 source is introduced and adsorbed on Si substrate and then Ar gas purges this source gas. Continuously, NH3 gas in supplied into reaction chamber and adsorbed on the Ti-adsorbed Si substrate and then Ar gas is again introduced to purge NH3 gas. These four steps are one cycle. The main variables in this experiment are source pulse time, source purge time, reactant pulse time, reactant purge time, and so on. The deposition characteristics are also different depending on substrate temperatures. Above the thermal decomposition temperatures, the film thickness is a function of the source pulse time like conventional CVD. Below the thermal decomposition temperatures, the film thickness is saturated and exhibits a constant value in this temperature range. The TiN film thickness depends only on the number of deposition cycle. The process window were determined by experimentally in this temperature range. Process variables were established, and then TiN films were deposited. The characteristics of this TiN diffusion barrier were analyzed. The surface microroughness, the chemical composition and contaminant contents were measured by AFM, SEM and AES. A crystal structure and the phase identification were performed with using XRD and the sheet resistance was measured by a four point probe. These results will be discussed and compared with the results of TiN formed by sputtered and conventional CVD methods.

TiN film is used as a diffusion barrier layer in contact and via holes in the metallization process of the microelectronics. In most cases, TiN film has been prepared by sputtering which has limited conformality. With the shrinkage of the dimension of the device structure there has been an urgent request for new deposition methods which offer better conformality. Recently, modified PVD systems like highly ionized sputtering system and CVD systems like MOCVD and PECVD systems have been developed.

We prepared TiN films with TIC4, N2, and H2 in an ECR PECVD system. TiN films prepared at the temperature of 450°C had resistiveity lower than 50 μm Ω cm and better step coverage than those prepared by PVD system. Barrier properties of the TiN films against Cu were investigated and related with the film properties like composition and microstructure.

The Cu/TiN/Si structure were annealed in an H2/Ar atmosphere for 30 min at the temperature range from 500 to 600°C.

Plasma treatment and thermal treatment during and/or after the deposition in various atmosphere were adopted to change the composition and the microstructure of the TiN films.

The composition of the film was analyzed with AES, the microstructure of the film was observed with SEM and the crystallinity was analyzed with XRD. The electrical resistivity was measured with four-point probe method. Barrier properties of the films were studied again Cu metallization. The change in the resistivity and the structure of the Cu/TiN/Si were investigated after the heat-treatment.

Low resistivity (∼15μΩ-cm) TiSi2, CoSi2 and NiSi lines have been shown to be thermally stable and show no linewidth dependence after ∼850°C, 800°C and 700°C/1 hour annealing on poly-Si (B, As, and P-doped) with linewidths down to ∼0.43, 0.42 and 0.15 μm. Better thermal stability of silicides might be correlated to the larger poly grains formed after high dose implant and post-implant anneal.

The effects of B and N addition on the phase transition and barrier performance of the plasma deposited W-B-N films are investigated. The W-B-N films have chemical compositions in the range from W67N33 to W38B42N20 corresponding to the flow ratio of B10H14/NH3. Among the films of various compositions of B and N, W46B25N29 film shows excellent thermal stability against the Cu diffusion because the W46B25N29 film keeps the amorphous state even after the annealing at 800°C for 30 min. Resonance backscattering and x-ray photoemission spectra for B and N atoms before and after the annealing process indicate that the amorphous state is retained due to the formation of the B-N bonds.

Titanium (Ti) and titanium nitride (TiN) films are widely used as barrier stack to prevent junction spiking. It is also an important material for an anti-reflection coating (ARC) on aluminum (Al) films to facilitate lithography processes during multilevel metallization for the manufacture of integrated circuits on silicon-based (Si) semiconductor devices. Secondary Ion Mass Spectrometry (SIMS) is proven to be very powerful analytical technique for the semiconductor materials. However, quantitative analysis of very thin structures using SIMS constitutes an ultimate challenge since a large fraction of the profile is located in the transient region where a stable concentration of primary beam species has not been established.

This paper reports a SIMS technique for advanced characterization of very thin titanium and titanium nitride layers. Improvements in depth resolution were achieved by reducing the angle of incidence and the impact energy maintaining enhanced ionization yield associated with oxygen bombardment. Significant improvements in characterization of the film surface were developed by using oxygen flooding technique. Optimized oxygen pressure was used to achieve a stable ion yield due to the complete surface oxidation of titanium and titanium nitride layers during the analysis. The method was employed in the SIMS characterization of multiple Ti/TiN films deposited on silicon substrate. The example presents dramatic enhancement in depth resolution due to minimized matrix related ion yield variations at the interfaces.

With an increasing component density and shrinking feature size in integrated circuit (IC) chips, the heat dissipation issue on the IC chips becomes increasingly important because of device performance and reliability concerns. The heating behavior at Ni/doped-Si junctions, which depends on Joule heating, Peltier effect and heat conduction, is explored in the study. A semiconductor-on-insulator (SOI) structure is used to obtain thermal isolation of the test specimen. The Si channel of 720 μm × 25 μm was lithographically defined and implanted with As+ and BF2+ dopants at a dose of 5×1015 ions/cm2, respectively. By applying a current through a Ni contact/doped-Si/Ni contact structure and measuring the resistance of the doped Si channel near the cathode and the anode ends, we found an obvious asymmetrical heating behavior at the two ends, depending on the dopant type and post-implanatation annealing condition. The Seebeck coefficients of doped Si were measured to be about 140 μV/K and 80 μV/K for BF2+ - doped Si and As+-doped Si, respectively.

The recently developed oxide mediated epitaxy (OME) technique involves the growth of epitaxial CoSi2 through a thin layer of silicon oxide grown in peroxide baths. Here we report improvements of the OME technique from the use of in-situ grown thermal oxide as the barrier layer and post-growth oxygen anneals. Growth of uniform epitaxial CoSi2 layers by OME on non-planar surfaces of selectively deposited CVD Si layers with oxide and nitride patterns was also demonstrated. Both the epitaxial orientation of CoSi2 and the thickness of the CoSi2 layer, measured along the deposition direction, remained unchanged across facet boundaries. OME appears well suited for shallow-junction silicidation application in devices involving raised source/drain structures.

Electroless cobalt-rich CoWP ternary alloys with a low weight percent of tungsten (∼ 2 percent) and a high phosphorus content (∼11 weight percent) have been deposited in basic solution onto copper and cobalt in integrated Cu damascene structures. A capability of the electroless CoWP deposition to form conformal barrier/protection films was demonstrated. Conformal 10 nm thick CoWP layer was also formed on the sidewalls of 30–40 nm wide seam of aspect ratio about 5:1 on the top of 0.4 μm wide in-laid Cu line.

The C54 phase formation process of titanium silicide was studied after selective chemical vapor despostion (CVD) onto very small silicon structures, to ascertain the efficacy of CVD to form low resistance contacts in sub-quarter micron technology. Because the selective CVD process forms silicide on any exposed silicon in a CMOS device, the process was studied on both polysilicon and Si (100) chips. The structures consisted of arrays of about 106 identical lines, 0.1 2.0 μm in width, depending on the chip. The CVD process employed TiCl4 and SiH4 for the most part as process gases and the depostion temperature ranged from 730–825°C. X-ray diffraction (XRD) was used to document the amount of C54 phase present after deposition. In some cases samples were annealed after deposition and the phase transformation behavior studied by in-situ XRD. The latter technique employed a synchrotron radiation source providng for rapid XRD spectra collection, so that the C49-C54 phase transformation could be examined with great precision in real time during rapid thermal annealing. The results of CVD depositions were compared to titanium silicide formed by sputter deposition of Ti on identical silicon chips, followed by a typical salicide protocol. Although the phase formation is affected by both film thickness and substrate temperature during CVD, the general result is that the C54 formation is more facile using the CVD process, especially for the smallest line dimensions. The findings are discussed with respect to nucleation processes occurring during growth and post-deposition thermal processing.

Pd/Zn/Au contacts to p-In0.53Ga0.47As/InP with various barrier layers (Pd, Pt or LaB,) to the indiffusion of Au have been examined by Rutherford Backscattering Spectrometry (RBS). For the metallisations with a barrier layer of Pd, the ageing of the contacts at 400°C for 20 h produced a widespread indiffusion of Au. In comparison, the incorporation of a layer of Pt or amorphous LaB6 prevented an indiffusion of Au and significantly reduced any outdiffusion of the semiconductor elements. The presence of the barrier layer of Pt or LaB6 produced little or no detrimental increase in specific contact resistance, ρc, for this contact system. Values of ρc in the range 8–10 × 10−6 Ω cm2 were obtained for all of the contacts based on Pd/Zn/Au after annealing at 500°C. A comparison has been made with the characteristics of Pt/Ti/Pt/Au contacts to p-In0.53Ga0.47As/ InP which were shown as stable against the indiffusion of Au.

In this talk, we summarize the experimental results obtained on metal-GaN interactions in our laboratory. These interactions include the epitaxial growth of metal thin films on chemically cleaned GaN surfaces, metal silicides for Schottky contacts and metallization schemes for ohmic contacts. We found that many fcc and hcp metals can grow epitaxially on (0001) GaN surfaces at room temperature without in-situ surface cleaning. Metal silicide contacts (such as PtSi) may be more suitable for high temperature applications than elemental contacts, due to the thermal stability of silicides. The intrinsic mechanisms for ohmic behavior for various metal contacts are not well understood at present. More consistent barrier height values measured experimentally can shed light on this issue. Due to the defective nature of the GaN layers, carrier transport across the metal/GaN interface can be due to a number of transport mechanisms, thus making accurate determination of the barrier height difficult. In spite of these difficulties, it seems possible to draw certain general conclusions on the electrical behavior of metal contacts on n-GaN.

Owing to their large band gaps and high dielectric constants, III-V nitrides are very attractive for high temperature electronics and optoelectronic device applications. Improved material properties have recently led to a variety of devices being demonstrated such as blue, green, and yellow light-emitting devices as well as laser diodes, metal-semiconductor GaN based fieldeffect transistors (MESFETs), and AlGaN/GaN based high electron mobility transistors (HEMTs). The presence of parasitic resistance can significantly limit performance such as lower speed for electronic devices and higher turn-on voltage for the optical devices. There is room for improvements for both n- and p- type ohmic contacts in order to lower parasitic resistance and improve reliability. W based contacts on GaN and InGaN have been demonstrated and show excellent thermal stability, however the contact resistivity still in the range of 10−5 Ω-cm2. By using InN and graded InGaN as the contact layers, the contact resistivity can be reduced to ∼ 10−6 Ω -cm2.

Besides low resistance ohmic contacts, a low leakage current and high turn-on voltage gate contact is critical to high performance electronic devices. Nitride based materials are very inert to conventional wet chemical etching used for other III-V compound semiconductors. Currently, dry etching is widely used for the device fabrication, however, III-nitrides are sensitive to dry etching, especially in the step of the gate recess etching. In this talk, metal insulator semiconductor (MIS) gate contacts based on AIN and Ga2O3/Gd2O3 will be discussed.