Interconnect delay is believed to have a dominating impact on the speed of large logic circuits (such as micro-processors) when the Si technology is scaled into sub- 0.25um generations. In this paper, we analyzed interconnect scaling issues based on leading micro-processor trend data, simple RC delay model and the “Rents' rule”. It was concluded that, in order to not limit the speed of large logic circuits, “fat” metal wires need to be used for upper metal layers, which will lead to a rapid increase of required number of metal layers (>10) for sub-0.25um technology generations. Introducing Cu and low ε interconnect system can delay this rapid increase by ∼1 generation. Creating multiple clock frequencies in large logic chips and reducing the size of high frequency islands appears effective in containing the interconnection delay problem. Therefore, the proposed interconnection scaling/development strategy is to introduce Cu and low ε dielectric into manufacturing in next 1∼3 generation (0.25um∼0.13um), develop low cost and high yield interconnect system to enable ∼10 interconnect layers, and improve circuit design methodology to reduce high frequency island size.