We report on the epitaxial growth of CoSi2 on silicon using ion beam synthesis and molecular beam allotaxy. The latter process uses molecular beam epitaxy to grow a silicide precipitate distribution embedded in single crystalline silicon and thermal annealing to form the epitaxial layer. Both, ion beam synthesis and molecular beam allotaxy, are capable to grow epitaxial buried and surface CoSi2 layers on Si(100) and Si(111) of high quality.

The thermal stability of thin CoSi2 layers is demonstrated to improve with the use of oxygen-containing annealing ambients. Layer agglomeration in epitaxial and polycrystalline CoSi2 layers grown on single crystal Si and polycrystalline CoSi2 layers grown on α-Si was retarded by oxygen annealing. A thin SiO2 layer grown during oxygen anneals which curbs surface diffusion and reduces the rates of kinetic processes is thought to be the primary reason for the improvement in CoSi2 thermal stability.

Local oxidation of thin cobaltdisilicide layers (10–30 nm) allows patterning with distances between silicide pads as small as 70 nm. The epitaxial silicide layers were grown by molecular beam allotaxy (MBA) on Si(100) substrates. They were characterized by TEM, RBS and sheet resistance measurements showing good crystal quality and excellent thermal stability up to 1200°C. Similar to the well established technology for local oxidation of silicon (LOCOS), the silicide layer was caped by 20 nm SiO2 followed by 300 nm of Si3N4. The nitride was patterned by optical lithography and dry etching. During dry oxidation at temperatures ranging from 900°C to 1000°C SiO2 is formed on the unprotected areas of the silicide. The Co atoms diffuse from the SiO2/CoSi2 interface to the CoSi2/Si interface to form CoSi2. Near the edges of the nitride mask the silicide layer thins and finally separates. Two metallic pads electrically separated by Si and SiO2 with a gap of 70 nm were produced this way. Monte Carlo simulations of the process revealed that the reason for the separation is stress dependent diffusion due to the stress induced by the nitride mask. The stress dependence of the separation process was experimentally verified using different nitride thicknesses. SEM and TEM studies showed perfect lateral patterning. This patterning process could be used in the fabrication of MOSFET's with ultrashort gatelengths.

The thickness dependence of the reaction of cobalt with silicon and epitaxial silicongermanium alloys (SiGe) was studied. Cobalt layers 25 Å and thicker deposited on Si(100) and annealed at 600°C formed CoSi2. When the thickness of the Co film was reduced to 10 Å the Co/Si(100) reaction resulted in a mixture of CoSi and CoSi2 even after annealing for 20 minutes at 800°C. The products of the reaction of Co with (100)-oriented Si1−x Gex after annealing at 800°C depended on the thickness of the Co film and the Ge concentration in the SiGe layer. When the thickness of the Co film was below a critical value, the only phase formed during the Co/SiGe reaction was CoSi. A mixture of CoSi and CoSi2 was observed when the thickness of the Co film exceeded the critical value. The critical thickness for CoSi2 nucleation increased superlinearly with Ge concentration in the range 0≤x≤0.25, and did not depend on the doping of the Si(100) substrate or the strain state of the SiGe film. XRD and EXAFS measurements indicated no measurable incorporation of Ge had occurred in either the CoSi or CoSi2. The amount of CoSi2 formed above the critical thickness increased monotonically with the thickness of the as-deposited Co film. The observed thickness effect was attributed to preferential Co–Si bonding in the reaction zone, and was modeled in terms of the energy cost of Ge segregation, which accompanies the formation of CoSi and CoSi2 during the reaction of Co with SiGe.

Silicide technology using cobalt-titanium alloy has been developed for sub-quarter micron devices. Extremely flat and epitaxial CoSi2 films are successfully grown on a (100) Si substrate. Improved SALICIDE process is not influenced by native oxide on a Si surface. This technology will be very useful in deep sub-quarter micron devices.

A NiSi-based self-aligned silicidation (SALICIDE) process has been integrated into a 0.25 Ion CMOS technology. It involves rapid thermal annealing (RTA) of Ni thin films (300, Å thick) on Si substrates in the temperature range ≈400 - 700 °C. It was found that the NiSi sheet resistance (Rs) gradually decreases with decreasing linewidth. Parameters, such as RTA temperature, substrate dopant (As vs BF2) and structure (single crystal vs poly), were found to have little effects on Rs. NiSi forms a smoother interface with single crystalSi than with poly Si, and has a slightly lower resistivity. MOSFETs based on NiSi show comparable device characteristics to those obtained with Ti SALICIDE. Upon thermal annealing, NiSi remains stable at 450 °C for more than 39 hours. The same is true for 500 °C anneals up to 6 hours, except for NiSi narrow lines (<0.5 μm) on n+ poly Si substrates whose Rs is moderately increased after a 6 hr anneal. This work demonstrates that with an appropriate low-thermal budget backend process, NiSi SALICIDE can be a viable process for deep submicron ULSI technologies.

The role of strain on the thermal stability of NiSi has been studied by deposition and annealing of Ni on strained and relaxed Si(100) n-type substrates. Strained Si substrates have been produced by depositing a pseudomorphic silicon film on top of a 3000 Å thick relaxed Si0.8Ge0.2 film. Raman spectroscopy has proved the top silicon film to be strained. The presence of the characteristic hatch-cross pattern has been confirmed by Atomic Force Microscopy (AFM). Scanning electron microscopy (SEM) and Photoelectron emission microscopy (PEEM) show that the islanding of the NiSi film appears at lower temperature on the bulk silicon substrate (600°C) than on the strained silicon substrate (700°C). The improved thermal stability of NiSi on strained Si can be explained by the difference in relative interface energy of NiSi on strained and relaxed silicon. The thermal expansion coefficient of Ni being 3 times larger than that of Si, NiSi is in compression on Si at 500°C already. The correlation of this compression state with the lattice parameters of bulk and strained Si (100) produces an increased NiSi islanding probability on bulk Si (100) with respect to strained Si.

The Nd-disilicide, which exists only in a tetragonal or an orthorhombic structure, cannot be grown epitaxially on a Si(111) substrate. However, by adding Y and using channeled ion beam synthesis, hexagonal Nd0.32Y0.68Si1.7 epilayers with lattice constant of aepi = 0.3915 nm and cepi = 0.4152 nm and with good crystalline quality (χmin of Nd and Y is 3.5% and 4.3 % respectively) are formed in a Si(111) substrate. This shows that the addition of Y to the Nd-Si system forces the latter into a hexagonal structure. The epilayer is stable up to 950 °C; annealing at 1000 °C results in partial transformation into other phases. The formation, the structure and the thermal stability of this ternary silicide have been studied using Rutherford backscattering/channeling, x-ray diffraction and transmission electron microscopy.

In view of its low barrier height to n-type Si, ErSi2 has potential applications as an infrared detector, as low-resistance ohmic contacts and as source/drain regions in Schottky barrier MOSFETs. Although there is a substantial body of work on ErSi2 grown on Si(111), there are relatively few published papers on the growth and properties of ErSi2 on Si(100). In order to develop a CMOS-compatible process, we have studied the growth of ErSi2 using a multi-source, UHV magnetron system to sputter-deposit 20 nm Ti/(10–50) nm Er bilayers on chemically cleaned n-Si(100) substrates followed by ex-situ rapid thermal annealing in N2. Highly oriented ErSi2 in the hexagonal phase was formed at an annealing temperature of 400°C with ErSi2 (100) Si(100). The Ti overlayer and the unreacted Er were selectively etched in HF and HNO3, respectively, leaving behind an ErSi2 layer with a smooth surface morphology, a uniform bulk composition and a planar ErSi2/Si interface. Results of electrical sheet resistance and Schottky barrier height measurements on these layers will be reported.

The mechanism and evolution from the early stages of the Ti/Si reaction by rapid thermal processing (RTP) at 650°C in the presence of Mo doping was studied and compared to the case without Mo doping; for amorphous, polycrystalline and single crystal (100) Si substrates. It was found that for Mo doped polycrystalline Si or Mo doped amorphous Si, the low resitivity C54 TiSi2 phase nucleates at the Ti/Si interface and grows following diffusion limited kinetics, bypassing the nucleation of the high resistivity C49 TiSi2 phase. The conventional phase sequence, with C49 TiSi 2 nucleation and growth, was observed on Mo doped (100) Si and all samples without Mo. The mechanism of early C54 nucleation was identified by high resolution transmission electron microscopy (HRTEM): at early stages of the reaction, precursor silicide phases lattice matched to C54 TiSi2 nucleate at the Ti/Mo doped Si interface, and act as templates for epitaxial nucleation of C54 TiSi2. Two such phases were observed, MoSi2 and a phase with spacings of 2.26 Å and 4.2 Å. Image simulations suggest that the structure of the second template phase is based on Mo5Si3. Similar kinetics were observed on large structures and narrow lines for Mo doped Si (except for the case of (100) Si), indicating that this growth mechanism eliminates the linewidth dependence. Implementation on a 0.10 μm CMOS technology of a process combining Mo doping with pre-amorphization (PAI) achieves low source/drain (S/D) sheet resistance, and the first Ti salicide process with low gate sheet resistance down to 0.06 μm.

The mechanism of the narrow line effect in TiSi2, films on highly As-doped diffusion layers is studied by TEM observation of grains in the TiSi2. The narrow line effect is shown to be due to an enlargement of the TiSi2, grain size caused by regrowth of the pre-amorphized regions before the start of silicidation. Knocked-on oxygen from the SiO2 cover layers is found to delay the onset of the silicidation.

Effects of the C49-TiSi2 epitaxial orientation on the C49-to-C54 phase transformation rate have been studied for samples with different pre-amorphization implantation (PAI) conditions. The C49 epitaxial orientation to the Si(001) substrate is characterized by use of grazing-incidence X-ray diffraction (GIXD) measurements. We found that the PAl treatment suppresses the epitaxial growth of C49-TiSi2 on Si(001) substrates and the poorer orientational alignment of C49-TiSi2 causes a more rapid transformation to C54-TiSi2. We believe this suppression of epitaxial alignment is a possible mechanism to understand the effect of the PAl treatment on the C49-C54 transformation.

The kinetics of the C49-C54 polymorphic transformation in titanium disilicides thin films grown on amorphous Si substrate has been followed by sheet resistance and Infrared Spectroscopy measurements on both blanket samples and submicron lines. The transformation of a fine grained C49 films (davg=30 nm) into the C54 phase was complete after annealing for ∼300 s at a temperature of 700 °C in blanket samples and of 730 °C in submicron lines. The Avrami exponent decreases from n=3 in blanket films to n=l in stripes. The transformation time at a given temperature increases with decreasing linewidth in agreement with the nucleation density model. Infrared Spectroscopy shows no shift of the peaks of the C49 phonons going from blanket to patterned films, suggesting the lack of strain on TiSi2 patterned films. The different behavior between blanket and laterally limited samples has been explained in terms of the different surface energies.

The formation of C49 TiSi2 phase at high temperatures was investigated by adding the Zr contents in Ti-silicide film. Stabilizing the C49 TiSi2 phase which exhibits lower surface and interface energies than those of the C54 TiSi2 phase at high temperatures was expected to suppress the problems of Tisilicide, such as the phase transition and the film agglomeration. The thin films of Ti and Zr were codeposited (40 nm) on Si substrates in the dual e-beam evaporation system equipped with an ion pump and its base pressure of ∼5 × 10−9 torr. The amounts of Zr contents (5 and 10 atomic %) added on Tisilicide were monitored by in-situ quartz crystal monitor. Immediately after the deposition, this film was annealed by ex-situ vacuum furnace at temperatures between 600 °C and 900 °C in 100 °C increments. The identification of the phase and the chemical composition were investigated by XRD and AES, respectively. The surface and interface morphologies were examined using cross-sectional TEM. The phase transition temperature of TiSi2 was raised with increasing Zr contents. The agglomeration of TiSi2 film was also suppressed by adding Zr element and much improved interface morphologies were observed.

This work explores the effects of arsenic on rapid thermal chemical vapor deposition (RTCVD) of TiSi2. The films were deposited using TiCI4 and SiH4 on 100 mm oxide patterned silicon wafers selectively at temperatures ranging from 750°C to 850°C. Arsenic dose levels ranging from 3×1014 cm−2 to 5*times;1015 cm−2 at 50 keV were considered. Experimental results reveal that arsenic results in a resistance to TiSi2 nucleation and enhanced silicon substrate consumption. These effects are enhanced at higher arsenic dose levels and reduced at higher deposition temperatures. We propose an arsenic-surfacepassivation model to explain the effects.

The introduction of rapid thermal processing for silicide formation has triggered a lot of research to temperature uniformity and reproducibility in RTP systems. From the other side there has been the demand to make the process itself as robust as possible for temperature variations. Indeed the way the module is set up can open or close the thermal process window for silicidation. In addition to the temperature, the ambient control is to be taken into account. Although gasses are specified to a low level of contaminants, the RTP step needs to be optimized for optimal contaminant reduction. Besides, the process wafer itself can be a source of contamination. In this paper an overview will be given of the role of temperature and ambient during RTP on the silicidation processes. The effect of the wafer on ambient purity will be highlighted. It will be shown that the latter can also have an impact on other process steps in the interconnect technology.

PtSi is one of the most used silicides in infrared Schottky barrier detectors due to its low Schottky barrier to p-type Si ( Øb ∼ 0.23 eV). Control of the thickness and uniformity of the silicide layer is fundamental for a good infrared detector performance, since the silicide thickness has to be in the range of 3 to 8 nm. Such thin layers are usually made by evaporation of Pt followed by a furnace annealing. We will show different approaches for fabrication of utra-thin PtSi layers. In all of the processes, high-vacuum sputtering is used for Pt deposition and the silicidation is performed in a rapid thermal annealing system. Smooth and uniform Pt Si layers down to 3 nm thick are formed in this way. It will be shown that the controllability of the thickness during sputter deposition is not a critical issue and the deposition process has a large process window. Moreover, when taking an optimal approach, a large process window can also be found for the RTA step. The implementation of these approaches for device fabrication and some electrial results of diodes made with them will also be presented.

The C54 phase formation process of titanium silicide was studied after selective chemical vapor despostion (CVD) onto very small silicon structures, to ascertain the efficacy of CVD to form low resistance contacts in sub-quarter micron technology. Because the selective CVD process forms silicide on any exposed silicon in a CMOS device, the process was studied on both polysilicon and Si (100) chips. The structures consisted of arrays of about 106 identical lines, 0.1 2.0 μm in width, depending on the chip. The CVD process employed TiCl4 and SiH4 for the most part as process gases and the depostion temperature ranged from 730–825°C. X-ray diffraction (XRD) was used to document the amount of C54 phase present after deposition. In some cases samples were annealed after deposition and the phase transformation behavior studied by in-situ XRD. The latter technique employed a synchrotron radiation source providng for rapid XRD spectra collection, so that the C49-C54 phase transformation could be examined with great precision in real time during rapid thermal annealing. The results of CVD depositions were compared to titanium silicide formed by sputter deposition of Ti on identical silicon chips, followed by a typical salicide protocol. Although the phase formation is affected by both film thickness and substrate temperature during CVD, the general result is that the C54 formation is more facile using the CVD process, especially for the smallest line dimensions. The findings are discussed with respect to nucleation processes occurring during growth and post-deposition thermal processing.

A novel low temperature self-aligned Ti silicidation with Ge+ pre-amorphization implant (PAI) is presented. Compared to conventional high temperature PAI silicidation, the advantages of Ti salicidation at temperatures below the recrystallization of a pre-amorphized layer are: (1) C49 TiSi2 silicide formation occurs only in the pre-amorphized layer so that the silicide depth can be well controlled, forming a very sharp interface between the silicide and the Si substrate; (2) Ti just reacts with the amorphous layer, avoiding the so-called bridging issue in which the silicide grows laterally over the isolation or spacer; (3) the effects of metal thickness and substrate doping on silicide formation are suppressed.

To enable swift integration of process modules into manufacturable process flows; three components – individual process modules, their interactions and their variability-must be understood well. At dimensions ≤ 0.25 μm, this understanding is especially critical, and also quite challenging. We present here an approach to address this challenge by joint process design, using two key modules-salicide and source/drain-as an example. Together, these modules impact the silicide-to-diffusion contact resistance, (Rc), and the gate sheet resistance (Rs); which, in turn, significantly affect transistor series resistance and circuit delays respectively. We have built a model to help provide insight into the underlying physical mechanisms, and to help provide a quantitative framework for optimizing performance and variability. Rc, depends critically on the doping concentration immediately adjacent to the silicide, and this concentration is determined by the combined effect of silicide processing and the two-dimensional source/drain dopant profile. Rs depends on the thickness and phase of the silicide film formed, which, in turn, depend on the salicide process variables as well as the source/drain doping concentration, because both affect the silicide growth kinetics. Process conditions favoring Rs. and Rc are opposite to each other: thicker silicide films and higher thermal budgets help in the phase-transformation to the low-resistivity C54 phase and improve Rs but they increase dopant redistribution and worsen Rc. Optimal process design can improve the transistor drive current (Id) by ≈5%, and circuit performance, as measured by the figure-of-merit (FOM) by ≈ 4%. This improvement is significant, and an added benefit of this approach is that other transistor characteristics such as effective channel length, off-current, substrate current, etc. remain unchanged. In summary, we have demonstrated that by joint process design and integration of the salicide and source/drain modules, insight can be gained into the underlying physical mechanisms, and device and circuit performance can be improved significantly.