A modular approach to CMOS process development requires an understanding of individual process modules (channel, gate, etc.) and their interactions. The reverse short channel effect, (RSCE) in NMOS devices is one such interaction between the channel and source/drain (S/D) modules. Similarly the interaction between the S/D and silicide modules affects the contact and gate sheet resistance. This paper presents (a) an investigation of the effects of S/D processing (As and P implant conditions) on the RSCE, (b) effects of S/D and silicide processing on the contact and gate sheet resistance, (c) the use of an integrated system to optimize process modules and their interactions and (d) the validity of the modules and system in process development by obtaining a 4% improvement in drive current of a 0.25 micron NMOS device. The outputs of the S/D module include the doping profiles as a function of implant and anneal conditions. The interaction between the channel and S/D is caused by the damage created during the S/D implants, leading to channel dopant redistribution during subsequent thermal anneals. This interaction causes the RSCE in NMOS devices and has to be taken into account before the modules can be used for process optimization. The interaction is studied by varying the dose and energy of the As and P S/D implants and observing their effect of the RSCE. Further, to model this interaction, parameters of a 2D dopant profile model are extracted from device data and form a part of the S/D module in addition to the doping profile information. The system integrates the outputs from the process modules and their interactions and allows for a rapid search of the process space. The search criteria can be varied to include performance (e.g. drive and off current) and manufacturability criteria.

As CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

Copper alloyed with small amounts of aluminum or magnesium has recently been suggested as a promising material for interconnect applications in silicon integrated circuits. This work reports the results of the investigation of the electrical (capacitance-voltage and current-voltage) stability of the metal-oxide-semiconductor capacitor made with copper-0.5 at. % aluminum and copper-2 at. % magnesium as metal, deposited on thermally oxidized silicon substrates. Effect of thermal treatment in vacuum ambient before and/or during the electrical testing was investigated. The resistance to oxidation of these alloys was also investigated. The results show that copper magnesium, after a thermal treatment of 350°C or higher, produces a passivating layer at the interfaces that has excellent corrosion resistance and very stable behavior in terms of capacitance-voltage and current-voltage measurements. Copper aluminum performed adequately, much better than pure copper but was inferior to copper magnesium.

We have formed thin films of Cu3Ge on (100) Si and (100) Si50Ge50 for low resistivity ohmic contacts and interconnects by the sequential room temperature e-beam deposition of a layer of amorphous Ge, followed by a polycrystalline layer of Cu. We have also deposited thin films of Cu on the Si50Ge50 to compare the behavior of films of Cu3Ge relative to that of pure Cu. We have determined by transmission electron microscopy (TEM) that films of Cu3Ge form an abrupt interface with Si and Si50Ge50, with no indication of interaction between the film and substrate. We have also shown by secondary ion mass spectrometry (SIMS) that Cu diffusion into the underlying substrate is not observed for films of Cu3Ge as compared to that of pure Cu. We have shown that Cu reacts with Si50Ge50 when annealed or 30 min. at 400°C to form a layer of Cu3Si1−xGe.. We have also observed that room temperature oxidation of the underlying Si50Ge50 does not occur as compared to the room temperature formation of SiO2 that is observed in Cu3Si/Si structures.

Copper was electroplated on sputtered Cu seed layer with Ta diffusion barrier. We achieved enhanced Cu deposition at the bottom of trenches/vias and defect-free filling sub-0.5 μm trenches (down to 0.25 μm width) of high aspect ratio (up to 4:1). Large grains occupying the entire trench were observed. Bottom step coverage of electroplated copper in sub-0.5 μm trenches was estimated to be about 140%, while sidewalls step coverage was about 120%. Via resistance for sub-0.5 μm vias was measured to be below 0.55 Ω. Strong <111> texture, large grains, and low tensile stress were observed in electroplated Cu films and in-laid Cu lines after low temperature anneal.

Preparation of Cu-0.3 at.% Al alloy films by homogenization anneals of metallic bilayers consisting of Cu/Cu-AI on SiO2 is studied to produce advanced copper based metallization for future ICs. The bilayer films were annealed at temperature in the range of 200°C- 400°C and the depth profiles were obtained using Rutherford Backscattering technique. It is found that Al diffuses through the undoped copper layer to surface - leading to lower Al concentration in the original Al doped Cu layer and apparently increased concentration of Al in undoped Cu (not detectable by RBS). The resistivity of these annealed films ranged from 2.1 to 2.4 μΩ-cm depending on final Al concentration achieved. Electrical stability of such MOS capacitors was also investigated. All these results will be presented and discussed showing that Al-doped copper layers can be used as diffusion barrier/adhesion promoter between the oxide ILD and copper metal.

We demonstrate the extendibility of the Cu damascene process to 0.1 μm wide lines. Cu interconnects, 0.1 - 1 μm wide, were fabricated by a damascene process that produced planarized lines and vias, imbedded in insulators. This process was defined by 1) trench and via formation in blanket dielectrics using e-beam lithography and reactive ion etching, 2) trench fill using a series of metal depositions, and 3) chemical mechanical polishing to remove the field metals. Physical vapor and ionized physical vapor deposition techniques were used to deposit the adhesion/diffusion barrier liner and the Cu seed layer, respectively. The main Cu conductor was deposited by an electroplating method. The width of lines and vias were varied from 0.1 μm to 1 μm while the thicknesses were held constant at 0.45 μm. A near bamboo-like structure was observed in the sub-μm wide lines. The effective resistivity of the Cu lines was found to be about 2.3 μΩ-cm and was independent of width after annealing at 400 °C.

The transition from Al to Cu for advanced ULSI interconnects involves changes in architecture and deposition technique that will influence the microstructure and texture of the metal. Cu interconnects are typically formed within the confines of pre-patterned trenches and vias using an electroplating process with a sputtered Cu conduction layer deposited over a refractory metalbased diffusion barrier layer. In this paper, we focus on the influence of the barrier layer (PVD Ti/TiN, Ta, TaN, CVD TiN) and the effect of a vacuum break between barrier and conduction layer depositions, on the texture of the Cu lines, as examined by X-ray diffraction pole figure analysis.

A preferred (111) orientation was observed for all samples. The samples with no vacuum break between barrier and conduction layer deposition exhibited in plane anisotropy that was particularly pronounced for the Ta and TaN samples compared with the Ti/TiN sample. Focused ion beam images and transmission electron micrographs showed Cu grain size to be on the order of the trench width with a high degree of twinning, and no boundary could be distinguished between the PVD Cu conduction layer and the electroplated Cu.

We present a Back-End Simulation Tool (BEST) developed to address important issues for modeling polycrystalline and multi-layered interconnect materials. During the temperature cycles of interconnect fabrication, diffusion and mechanical equilibrium processes are coupled. Accurate simulation of these systems leads to very large problems, and it is therefore necessary to partition the problem using a staggered scheme. We have developed an unconditionally stable algorithm which is crucial to the success of this approach. We are also able to consider the coupled effect of an electromigration driving force in conducting materials. In order to predict effectively the deformations and stresses which occur in structures fabricated from these materials, our work addresses the multiple length scales which characterize the problem. The simulations span from interconnect level structures to detailed descriptions of grain boundaries and material interfaces using continuously spatially varying material properties. The formulation naturally enforces segregation of impurities or vacancies (for metal self-diffusion) to and across interfaces and to surfaces. Our solutions of the coupled physical problems with the explicit inclusion of grain and layer structures make this a tool for efficient evaluation of the properties and reliability of new interconnect materials and layered structures. We will show some applications of our model to technologically relevant examples including hillock formation and interface stresses.

In an attempt to increase the deposition rate, new Cu (I) compounds, (hfac)Cu(1-pentene)(1) and (hfac)Cu(VTMOS)(2) have been synthesized. These species are chartreuse liquids and exhibit sufficient vapor pressures to allow high transport rates.

In order to avoid the premature decomposition of the copper precursors during CVD processes, the 50% of free 1-pentene, and VTMOS was added to the compounds 1 and 2 respectively. These mixtures 1 and 2 were used in this study. Approximately 2gm of precursor was used for each experiment. No premature decomposition of the precursor in the source reservoir was observed during CVD processes. It is a sufficiently important result to expect the use of these mixtures in copper CVD to achieve the reproducible deposition.

The copper films using these mixtures were deposited in a hot-wall pyrex reactor at a pressure of approximately 10–2 torr under dynamic vacuum. The films deposited at 100°C, 150°C and 200°C from the mixture 1. Pure copper films were deposited from these species. The resistivities 1.8 ∼ 2.1 μΩcm were obtained in the deposition temperature range. SEM revealed that the surface morphology of the films grown in these depositon temperature range was composed of dense film and grains were well connected. The deposition rate at 200°C was 3,500 Å/min.

We have investigated the effects of oxygen contamination on the agglomeration of thin Cu films fabricated by physical vapor deposition on Ta barriers. Thin Cu films on clean, ultrahigh vacuum-deposited Ta barriers were stable against agglomeration when annealed for several hours at temperatures as high as T=380°C. However, on Ta barriers intentionally contaminated with oxygen, agglomeration of Cu films occurred within minutes when annealed above 300°C. Time-resolved reflectivity was used to study film evolution and agglomeration in situ. Atomic force microscopy was used for post-growth characterization of agglomeration. Characterization of Ta barriers by X-ray photoelectron spectroscopy and Rutherford backscattering spectrometry demonstrated that clean Cu films on contaminated Ta barriers containing as little as 5% oxygen were unstable against agglomeration.

The chemistry of Cu-CVD from the precursor (hfac)Cu(tmvs) on sputtered TiN films was investigated using a simple tubular reactor analysis. In the present study, the validity of a proposed reaction mechanism and its rate constants were investigated using a well characterized test structure (Macrocavity). The macrocavity was prepared by stacking silicon wafers with spacing ranging from 0.1–0.5mm, and placing the stacked structure in the tubular reactor. The growth rate profile within a macrocavity is simulated from a derived equation using the reaction mechanism and rate constants obtained from previous work. The variation of the absolute growth rate around the center of a macrocavity with varying wafer spacing indicates that the Cu deposition is proceeded via gas phase reaction to produce a reaction intermediate. As a whole, the simulated growth rate profiles agree very well the experimental data. Therefore, we conclude that the mechanism and reaction rate constants from our research are valid and can be applied to the prediction of growth rate of Cu from the (hfac)Cu(tmvs) system.

We have developed a solution delivery technique for performing copper CVD using the reduction of Cu(hfac)2 [where H(hfac) = 1,1,1,5,5,5-hexafluoro-2,4-pentanedionel. We have obtained deposition rates of up to 3.6 mg cm−2 hr−1 (ca. 60 nm min−1) for a deposition temperature of 300 °C and reactor conditions of 40 Torr H2, 12 Torr isopropanol, and 1 Torr Cu(hfac)2. The increased rates are several times faster than growth rates observed using conventional Cu(hfac)2 sublimation with pure H2 as the carrier gas. We compare growth rates and film microstructure using TiN- and WNx-coated substrates. We also give preliminary results showing how the partial pressures of H2, i-PrOH, and Cu(hfac)2 each influence the deposition rate.

Amorphous Ti-Si-N thin films are effective barriers to Cu diffusion in integrated circuits that use Cu interconnects. These films are believed to fail as diffusion barriers due to crystallization and subsequent diffusion of Cu along grain boundaries. We prepare thin films of Ti-Si-N by RF magnatron co-sputtering of Ti and Si in Ar/N2. Ti-Si-N films with Si concentrations of 6 to 22% have resistivities <500μΩ-cm. In previous reports we have shown that Si pn-junction diodes metallized with 20nm Ti40Si15N45/Cu do not fail (increased reverse leakage current) until 600%C. When annealed, these films crystallize to yield TiN and Si3N4. In this work we have studied the effect of oxygen on the degradation of the barrier via TEM, diode I-V measurements, and RBS. Oxygen incorporated into the film deposition process improves the barrier effectiveness as measured by diode I-V reverse leakage current. We find no correlation between the amount of O2 in the process gas feed stream and the film composition with O resonance analysis (RBS) or crystallinity (TEM).

For Co salicide process, a TiN cap layer is widely used to prevent oxidation of Co layers during silicidation by RTA. In this study, N2/H2 mixture ambient is used to eliminate the need for the TiN cap layer. The sheet resistance for the sample fabricated by N2 RTA without TiN cap layer shows large standard deviations for narrow N+ diffusion layers and shows 20% higher values and large standard deviations for P+ diffusion layers. On the other hand, the samples with N2/H2 RTA provides the same low and stable sheet resistance as those of the samples with TiN cap layer. XPS analysis shows that N2/H2 RTA suppresses oxidation of Co during the 1st RTA because of reduction by H2. B impurity in PMOS regions is known to retard silicidation of Co at 500°C. The retardation of silicidation seems to enhance oxidation of Co in PMOS regions by residual oxygen in the RTA chamber.

Atomic layer deposition(ALD) of amorphous TiN films on SiO2 between 170°C and 210°C has been investigated by alternate supply of reactant sources, Ti[N(C2H5CH3)2]4 [tetrakis(ethylmethylamino)titanium : TEMAT] and NH3. Reactant sources were injected into the reactor in the order of TEMAT vapor pulse, Ar gas pulse, NH3 gas pulse and Ar gas pulse. Film thickness per cycle was saturated at around 0.5 nrm/cycle with sufficient pulse time of TEMAT at 200°C. The ideal linear relationship between number of cycles and film thickness is confirmed. As a result of surface limited reactions of ALD, step coverage was excellent. Particles caused by the gas phase reactions between TEMAT and NH3 were almost free because TEMAT was separated from NH3 by the Ar pulse. In spite of relatively low substrate temperature, carbon impurity was incorporated below 4at%.

Refractory metal gates have been studied for CMOS gate electrodes on ultra thin gate oxide due to its midgap work function, low resistivity and no gate depletion, etc. In particular, titanium nitride received most attention because of its process maturity and its good diffusion barrier properties for backend applications. Different TiN film properties are important when TiN is used as a gate material than when it is used for backend applications. One issue is the effect of TiN film impurities on the gate oxides and their high temperature stability since some high temperature processes are usually needed after gate formation. This paper reports the study of different TiN films used as MOS gate electrodes on ultra thin gate oxide and the effects of their impurities on gate oxide electrical performance. PVD TiN films deposited with different process conditions show different oxygen content, and different gate oxide properties were observed when these PVD TiN films were used as gate electrodes. On the other hand CVD TiN films deposited using different precursors also showed different impurities, including carbon, oxygen or silicon, which largely affect CVD TiN performance when used as gate material. The different TiN films were characterized by X-ray glancing angle reflection, XPS, SIMS and TEM, and the electrical properties were studied by I-V, C-V, charge to breakdown (Qbd) and ramp voltage breakdown tests on MOS capacitors. The results showed that the high purity TiN films provide stable gate material with small damage to the gate oxide, but impurities, especially oxygen, affect the gate oxide properties after high temperature anneal. However, due to the different TiN process capabilities, TiN films with impurities may still have advantages over pure TiN film in some cases of different MOS gate applications.

The formation of TiSi2 films by chemical vapor deposition was investigated for the application as a contact plug material because of its low resistivity, low contact resistance with n+ and p+ Si, and good chemical stability with Si. TiI4 and SiH4 were used as source gases. Since TiI4 is thermodynamically less stable than TiCl4, the deposition temperature of TiSi2 with TiI4 precursor could be lower than that of TiSi2 from TiCl4 precursor. TiSi2 thin films with C49 phase were formed at 650°C on Si (100) wafer, while a Ti5Si3 phase was formed at 650°C on SiO2 substrate. The resistivity of the C49 phase films was 210 μΩ-cm. The C49 phase was completely transformed into a C54 phase above 800°C annealing in an N2 atmosphere and the resistivity reduced to 34 μΩ-cm. We were able to deposit TiSi2 films at lower temperature using TiI4 precursor, compared to TiCl4 precursor. The Cl and HCI byproducts originated from TiCl4 can be excluded using TiI4 precursor.

To study the effect of pre-treatment of substrates on the deposition behavior of Al films, the surfaces of TiN and SiO2 substrates were exposed to hydrogen plasma or Ar plasma before Al deposition. The Al films were deposited by the pyrolysis of dimethylethylamine alane (DMEAA). A uniform Al film was deposited by the hydrogen plasma exposure of SiO2 substrate, while island grains were grown by the Ar plasma exposure. The pre-treatments of TiN substrate did not affect the deposition rate of Al film. The concentration of OH radicals at the SiO2 surface was increased by the hydrogen plasma treatment. We suggest that the OH radicals enhance the adsorption of DMEAA on SiO2 surface, resulting in the larger number of nucleation sites.

Platinum is widely researched as the electrode material for capacitor of high dielectric films in dynamic random access memory (DRAM) application. However, the dry etching of Pt is difficult because of its chemical stability. So, the dry etching of Pt remains at the preliminary work.

In this work, Pt etching mechanism was investigated by using inductive coupled plasma (ICP) with Ar/Cl2/HBr gas.

The peaks were found due to brominated Pt as well as chlorinated Pt in the XPS (X-ray photoelectron spectroscopy) narrow scan. Ion bombardment effects on the etched surface decreased with increasing HBr/(HBr+Cl2) gas mixing ratio. The maximum etch rate of Pt was 105 nm/min at the HBr/(HBr+Cl2) ratio of 0. And selectivity to SiO2 was good in all samples with various HBr/(HBr+Cl2) gas mixing ratios. These results are consistent with XPS and OES (optical emission spectrometry) and single Langmuir probe.