The performance and cost of the logic ICs is more and more dominated by the interconnections. Reducing the capacitances in the advanced processes, especially with low k dielectrics, is a priority, while a differentiated approach can be applied for lowering the connection resistances, e.g. in adapting the interconnect material to specific levels. Integrating new materials leads to difficult trade-offs in order to achieve a good electrical performance of the circuit. Finally the increased number of levels of interconnection addresses other fields like integration density, defectivity reduction or cost.