Both a low resistance state and a high resistance state which were written by the voltage application in a local region of NiO/Pt films by using conducting atomic force microscopy (C-AFM) were observed by using scanning electron microscope (SEM) and electron probe micro analysis (EPMA). The writing regions are distinguishable as dark areas in a secondary electron image and thus can be specified without using complicated sample fabrication process to narrow down the writing regions such as the photolithography technique. In addition, the writing regions were analyzed by using energy dispersive X-ray spectroscopy (EDS) mapping. No difference between the inside and outside of the writing regions is observed for all the mapped elements including C and Rh. Here, C and Rh are the most probable candidates for contamination which affect the secondary electron image. Therefore, our results suggested that the observed change in the contrast of the second electron image is related to the intrinsic change in the electronic state of the NiO film and a secondary electron yield is correlated to the physical properties of the film.

A Magnetic Coupled Spin-torque Device (MCSTD) is a collective system of three interacting magnetic tunnel junctions (MTJs) that forms a novel magnetic logic gate. The fundamental principle of the MCSTD is the modification of the energy barrier for spin-torque magnetization switching of a central (output) MTJ device arising from changes in the magnetic state of two input MTJ devices. The input MTJs are placed in close proximity of a few tens of nm of the output MTJ such that their magnetic fringing fields are strong enough (> 10 Oersted) to modulate the switching characteristics of the output device. By changing the magnetic states of the two input MTJs four possible net magnetic fields at the center MTJ can be generated. A single MCSTD thereby enables NAND, NOR and XOR operations. In this paper, the fabrication of a prototype MCSTD device is described and preliminary experiment results are reported.

Metal/high-k dielectric core shell nanocrystal memory capacitor was demonstrated. This kind of MOS memory shows good performance in charge storage capacity, programming and erasing speed. By using a self-assembled Block Co-Polymer, Co/HfO2 core shell nanocrystals were well arrayed and showed uniform dot size and inter distance between dots. Compared with traditional metal nanocrystal fabrication process with E-Beam Evaporation followed by RTA (Rapid Thermal Annealing), core shell nanocrystal memory prepared by Block Co-Polymer produces a wide memory window of 8.4V at the ±12 V voltage sweep. Co/HfO2 core shell nanocrystals prepared by low-temperature Block Co-polymer process ensure high reliability of the devices.

We present a novel scalable and stackable nonvolatile solid state memory. Each cell consists of a storage element, based on phase change memory (PCM) element, and an integrated selector, using an Ovonic threshold switch (OTS). The cell is implemented to enable a true cross-point array. The main device characteristics and behaviors, corresponding physical processes in different operation modes, and key material properties are discussed.

Recently the Flash Memory is scaling limit, Thus the Memory of various types is now under study for the next generation large capacity nonvolatile memory. Resistance random access memory (ReRAM) is attracts much attention due to its advantage for integration in the next generation nonvolatile memory, because it is depend on scaling by lithography compared with the Flash Memory of capacity type. The material for ReRAM is classified roughly into binary oxides and perovskite oxides. Several binary oxides such as a TaOx have the advantage for low-temperature process and low-cost materials compared with perovskite oxides such as a (Pr,Ca)MnO3 (PCMO). In this study, TaOx film with the thickness of 10nm were prepared by reactive RF magnetron sputtering on 8inch-Pt/Si substrate using a Ta metal target in oxygen ambient. The sputtering system was the multi chamber type mass production tool. The TaOx thin film was amorphous phase as a result of measurement by X-ray diffraction meter. Ta top electrodes with 50 um diameters were deposited on the surface of TaOx layer by the DC sputtering method using a shadow mask. The “Forming” voltage of TaOx-ReRAM was 5.0V. After “Forming” process, the “Set” and “Reset” voltage were 3.0V and –3.0V respectively. It has good switching properties with large on/off resistance ratio above 1,000.

The usage of organic materials in the manufacture of electronic polymer memory devices is on the rise. Polymer memory devices are fabricated by depositing a blend (an admixture of organic polymer, small molecules and nanoparticles) between two metal electrodes. The primary aim is to produce devices that exhibit two distinct electrical conductance states when a voltage is applied. These two states can be viewed as the realisation of non-volatile memory. This is an interesting development; however, there are a number of theories that have been proposed to explain the observed electrical behaviour. We have proposed a model that is based on electric dipole formation in the polymer matrix. Here, we investigate further the proposed model by deliberately creating electric dipoles in a polymer matrix using electron donors (8-Hydroxyquinoline, Tetrathiafulvalene and Bis(ethylenedithio)tetrathiafulvalene) and electron acceptors (7,7,8,8-Tetracyanoquinodimethane, Tetracyanoethylene and Fullerene) small molecules.

Two types of structures were investigated (i) a metal/blend of polymer and small molecules/metal (MOM), device and (ii) a metal/insulator/blend of small molecules and polymer/semiconductor (MIS) architecture. A blend of polymer and small organic molecules was prepared in methanol and spin-coated onto a glass substrate marked with thin aluminium (Al) tracks; a top Al contact was then evaporated onto the blend after drying - this resulted in a metal-organic-metal structure. The MIS structures consisted of an ohmic bottom Al contact, p-type Si, a polymer blend (two small organic molecules and insulating polymer), followed by polyvinyl acetate and finally a top, circular Al electrode. In-depth FTIR studies were carried out to understand the observed electrical behaviour. An electrical analysis of these structures was performed using an HP4140B picoammeter and an HP 4192A impedance analyser at a frequency of 1 MHz.

In this work, an individual Ge island on top of silicon dioxide layer has been charged by a conductive EFM tip and quantitatively characterized at room temperature. Electrons or holes were successfully injected and were trapped homogenously in the isolated nano-scale Ge island. In order to quantitatively study these trapped charges, a truncated capacitor model was used to approximate the real capacitance between the tip and island surface. The analytical expression of the quantity of trapped charges in isolated Ge island as a function of the EFM phase signal was deduced. Applying a tip bias for -7V during 30 seconds leads to an injection about 800 electrons inside an individual Ge island.

The growth of GaN-QDs by radio frequency plasma assisted molecular beam deposition (RF-MBD) on thin SiO2 films for non-volatile memories (NVM) applications is demonstrated. Thermal budget modification during the deposition allows tuning of the size and density of the QDs. Preliminary electrical characterization of GaN-QD MOS devices reveals efficient electron injection at very low voltages from the Si accumulation layer to the QDs. The observed limitation in hole injection relates adequately to the energy band diagram of the structure.

The effect of thermal treatments in oxidizing ambient on the structural and electrical properties of low-energy Si-implanted thin SiO2 layers which previously suffered or not high temperature annealing in inert ambient was investigated. Based on TEM examination, charge trapping evaluation and FN conduction analysis of the resulting Si-NC SiO2 matrices, a model taking into account the healing of excess silicon atoms introduced by implantation and the generation of Si interstitials by oxidation above and below the viscoelastic temperature of SiO2 is proposed.

In this report, electrical properties of an organic memory device with a tri-layer structure, MoO3 nano-clusters layer sandwiched between Alq3 thin films, are investigated. The device using this kind of structure exhibits a large ON/OFF density current ratio over 104, long retention time over 1hr, and an electrically programmable character. The formation of the bistable resistance switching of the device originates from a charge trapping effect of the MoO3 nano-clusters layer. Moreover, current density-voltage (J-V) characteristics of the device are quite different from those of OBDs using MoO3 nano-particles. No negative differential resistance is observed in the J-V curve of the device. This may be due to the distinct surface morphology of the MoO3 layer on the Alq3 thin film.

On the road to miniaturization, nanocrystal layers are promising as floating gate in nonvolatile flash memories. Although much experimental work has been devoted to the study of these new memory devices, only few theoretical models exist to help the experimentalists to understand the physical phenomena encountered and explain the behavior of the device.

We have developed a model based on the geometrical and physical properties of the elementary structure of a nanocrystal flash memory, i.e. one nanocrystal embedded in an oxide between the channel and the gate electrodes. To obtain a fine analysis of the observed phenomena, several specific hypotheses have been taken into account. Concerning the channel, the contribution of the subbands is explicitly included. In the case of an electrode with a quasi-continuum of energy levels, we replace the continuum by equivalent sets of 2D subbands in order to be able to isolate the energy range that really contributes to the charging/discharging of the nanocrystal. The properties of the materials (bulk band structure, dielectric permittivity, …) can be easily set as well as the geometrical specifications of the elementary structure (nanocrystal radius, tunnel and control oxyde thicknesses, …).

The behavior of a layer of nanocrystals is described according to a statistical approach starting from single nanocrystal results. This method allows us to take into account the fluctuations of geometrical parameters. Thus we are able to simulate various types of materials for the nanocrystals (Si, Ge, …), the oxide layer (SiO2, HfO2, …) and the electrodes, for both a single nanocrystal and layers of nanocrystals.

We have fabricated and characterized ferroelectric-gate TFTs using In-Ga-Zn-O (IGZO) or In2O3 as a channel material. The ferroelectric gate insulator used in this work is (Bi,La)4Ti3O12 (BLT). We observed normal n-channel transistor operation for both IGZO and In2O3-channel TFTs. However, a charge injection type hysteresis was observed for IGZO channel TFTs in drain current – gate voltage (ID-VG) characteristics. Post fabrication anneal at 300oC reduced the charge-injection-tyoe hystereesis and the subthreshold swing was also improved from 0.27 to 0.19 V/decade. On the other hand, when the In2O3 was used as a channel, hysteresis due to the ferroelectric gate insulator was clearly observed in ID-VG characteristics. A memory window of 2V, a subthreshold voltage swing of 0.35V/decade, a field-effect mobility of 1.6 cm2/Vs, and a on/off drain current ratio of more than 10^6 were obtained.

We have investigated the resistance switching effect in Cu nanogap junction. Nanogap structures were created by means of electromigration and their electrical properties were measured in a high vacuum chamber. The measured current-voltage characteristics exhibited a clear negative resistance and memory effect with a large on-off ratio of over 105. The estimation from I-V curves indicates that the resistance switching was caused by the gap size change, which implies that the nanogap switching (NGS) effect also occurs in Cu electrodes, a popular wiring material in an integrated circuit.

In this work, we examine the influence of hafnium and zirconium oxides ALD precursor chemistry on the memory properties of SiO2/Si3N4/ZrO2 and SiO2/Si3N4/HfO2 non-volatile gate memory stacks. Approximately 10 nm thick ZrO2 and HfO2 layers were deposited on top of a SiO2/Si3N4 structure, functioning as blocking oxides. Both metal oxides were deposited using either alkylamides or cyclopentadienyls as metal precursors, and ozone as the oxygen source. In the case of the ZrO2 gate stacks a memory window of 6 V was determined, comprised of 4 V write window and 2 V erase window. Although no dramatic differences were evident between the ZrO2 layers, ZrO2 grown from alkylamide provided structures with higher dielectric strength. The memory structures with HfO2 blocking layers indicate that the memory window and the dielectric strength are significantly affected by the precursor. The structures with the HfO2 formed from alkylamide showed a write window of 7 V, while the films grown from cyclopentadienyl possessed window of 5 V. Comparison between the memory windows obtained using ZrO2 and HfO2 as control oxides reveals that the former provides memory structures with higher electron trapping efficiency.

A series of arrays consisting of Permalloy stripes with dimensions of 100 nm × 300 nm × 1500 nm was fabricated using electron beam nanolithography and magnetron sputtering followed by the lift-off process. In order to elucidate the effect of magnetostatic interactions among nanosized stripes on magnetic properties of the arrays, the separation between the stripes in different arrays was varied in the range between 100 nm and 2000 nm. Magnetic hysteresis loops of the arrays were measured using SQUID magnetometer for different orientations of the applied field with respect to the arrays. Magnetic anisotropy of the arrays was determined based on ferromagnetic resonance measurements at 9.8 GHz using EPR spectrometer. The measurements were carried out for different directions of in-plane magnetic bias filed. The angular dependence of the resonance field of the main resonant peak indicated presence of the uniaxial magnetic anisotropy due to elongated shape of the stripes. Comparison between angular curves of resonant fields for different arrays leads to the conclusion that increasing strength of magnetostatic interactions among the stripes leads to a suppression of the uniaxial anisotropy. The stripes separated by 2000 nm behave almost like non-interacting objects, but the effect of interactions becomes particularly significant for separations smaller than 600 nm. The properties of the arrays with the smallest separations resembled those of continuous films. Magnetostatic modes have been observed in the FMR spectra in addition to the main resonant peak. These modes are believed to result from dimensional confinement of lateral spinwaves in the magnetic stripes. No such modes were observed in the reference samples of solid Py films, with the in-plane applied magnetic field.

This paper presents the implementation of indium gallium arsenide field-effect transistors (InGaAs FETs) as non-volatile memory using lattice-matched II-VI gate insulator and quantum dots of GeOx-cladded Ge as the floating gate. Studies have been done to show the ability of II-VI materials to act as a tunneling gate material for InGaAs based FETs, and GeOx-cladded Ge quantum dots having the ability to store charges in the floating gate of a memory device. Proposed structure of the InGaAs device is presented.

Admittance spectroscopy measurement has been performed on NiOx thin films with various oxygen compositions (x=1.0-1.2) in order to characterize localized defect levels. The activation energy and concentration of localized defect levels in NiOx films with low oxygen composition (x≤1.07) are 120-170 meV and lower than 2×1019 cm-3, respectively. From I-V measurement of the Pt/NiOx/Pt structures, samples with high oxygen composition (x≥1.10) did not show resistance switching operation, while samples with low oxygen composition (x≤1.07) did. The best oxygen composition of NiOx thin films turned out to be 1.07 in order to realize repeatable and stable resistance switching operation.

The fabrication of Si nanocrystals (NCs) in multilayer structures based on HfO2 and alloys for memory applications is carried out using an innovative method, the ultra-low energy (1 keV) ion implantation followed by a post-implantation annealing. Si+ ions are implanted into SiO2 thin layers deposited on top of thin HfO2-based layers. After annealing at high temperature (1050°C), the implantation leads to the formation of a two dimensional array of Si NCs at a distance from the surface larger than expected, due to an anomalous oxidation of the implanted Si. Nevertheless, the best memory windows are obtained at lower thermal budget, when no nanocrystals are present in the layer. This suggests that electrical measurements should always be correlated to structural characterization in order to understand where charge storage occurs.

Resistive switching memory (RRAM) is attracting a strong interest as novel nonvolatile memories for high-density storage. Anyway this technology has to overcome two main issues before its use in real applications which are the high current needed for program operations and data retention stability. These two problems are here investigated from experimental and theoretical points of view to clarify the possibilities of NiO RRAMs to become a real competitive alternative to mainstream Flash technology.

This paper overview recent research results about ferroelectric FETs such as a Ferroelectric (Fe-) NAND flash memory for enterprise SSDs and a Ferroelectric 6T-SRAM for 0.5V operation low-power CPU and SoC.

In the last five years, as the data through internet increases, the power consumption at the data center doubled. To solve the power crisis SSD is expected to replace HDD. For such an enterprise SSD, the Fe-NAND flash memory is most suitable due to a low power consumption and a high reliability. The Fe-NAND is composed of Metal Ferroelectric Insulator Semiconductor transistors. The program/erase voltage decreases from 20V to 6V. In the Fe-NAND, the electric polarization in the ferroelectric layer flips with a lower electric field and the Vth of a memory cell shifts. Due to a low program/erase voltage, a low power operation is achieved. In the Fe-NAND, a high write/erase endurance, 100Million cycle, four orders of magnitudes higher than the conventional NAND, is realized because there is no stress-induced leakage current.

The Fe-NAND flash memory with a non-volatile (NV) page buffer is also proposed. The data fragmentation of SSD in a random write is removed by introducing a batch write algorithm. As a result, the SSD performance can double. The NV-page buffer realizes a power outage immune highly reliable operation. In addition, a zero Vth memory cell scheme is proposed to best optimize the reliability of the Fe-NAND. The Vth shift caused by the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively. A 1.2V operation adaptive charge pump circuit for the low voltage and low power Fe-NAND is introduced. By using Fe-FETs as diodes in the charge pump and optimizing the Vth of Fe-FETs at each pump stage, the power efficiency and the output voltage increase by 143% and 25% without the circuit area and process step penalty.

Finally, a ferroelectric 6T-SRAM is proposed for the 0.5V operation low power CPU and SoC. During the read/hold, the Vth of Fe-FETs automatically changes to increase the static noise margin by 60%. During the stand-by, the Vth increases to decrease the leakage current by 42%. As a result, the supply voltage by 0.11V, which decreases the active power by 32%.