The principal driver behind advanced hardware development in the communications and computer industries can be reduced to an optimal set of parameters related to performance, cost and reliability. High performance systems typically have high functional density. For example, the continuing trend of VLSI is toward reduced feature size, increased wiring density and larger chip size to achieve increasingly higher levels of on-chip functionality. At some point in the cost structure, however, the single chip solution is no longer viable, and monolithic integration gives way to hybrid integration. In this respect, the multichip module fills a void in the packaging/ integration hierarchy between the ever-larger single chip and the printed wiring board.

An analogous situation is emerging in optoelectronics. The single chip package with its relatively low system functionality and high cost is giving way to the multi-technology module that integrates optical and electronic functions within a single package. One of the most interesting approaches to the multi-technology module uses a silicon substrate as the platform for hybrid integration of electronics and optoelectronics. It will be argued that this “silicon waferboard” approach is the cost-effective route to manufacturability of high-performance modules for communications and computer systems. Enhanced reliability follows from applying standard IC processing technology at the platform level in the packaging hierarchy.

With advances in semiconductor technology straining the ability of packaging to keep pace, conventional electrical connectors cannot always meet emerging requirements in interconnection density and signal transmission speeds.

Connectors using flexible etched circuits (FEC) can provide interconnection densities of up to 200 lines per inch and high transmission quality for signals with 250-picosecond risetimes. A practical connector design meeting these density and speed goals depends on careful consideration of connector and system tolerances, ease of application, manufacturability, and material properties.

This paper discusses a practical approach to an FEC-based connector and the influence of material properties on connector performance.

A z-axis anisotropic electrically conducting polymer-matrix composite film was developed. It comprised 25 vol.% copper coated polyether sulfone particles and a polyimidesiloxane matrix. Each particle protruded from both sides of the film and provided a conducting path along the z-axis. A z-axis pressure of 40 kPa resulted in a z-axis electrical resistivity of 2 ohm.cm for the overall film (i.e., 5 × 10-2 ohm.cm for a conducting path); subsequent pressure removal caused the resistivity to rise to 7 ohm.cm only. The film exhibited negligible stress relaxation and a low modulus of 1.67 GPa.

An adhesive based interconnect design in which the contact force between a bumped die and substrate is maintained by the shrinkage stress of the adhesive was investigated for use in high performance applications. In general, heating will reduce the contact force because of the differential thermal expansions and load relaxation in the adhesive. Special experimental techniques have been developed to measure the relevant materials properties. The potential for optimization in terms of materials selection is discussed.

A three dimensional finite-element stress model was used to simulate the lead bending incurred during thermal cycling of a Flex connector joined to a silicon carrier via an eutectic solder. Three different coating conditions (no coating, with a polyimide coating, and with a silicone coating) were simulated. With the polyimide coating, lead bending was found to occur at the corner inner leads of the Flex as a result of the plastic strains accumulated there during thermal cycling. In the case of silicone, the corresponding plastic strains grew during the first thermal cycle but saturated subsequently, confirming the negligible lead bending observed experimentally. For the case of no coating, the highest plastic strain was found to be borne in part by the polyimide film at its edge and thus no significant bending was observed. In all cases, the results provided by the model agree well with the experimental observations.

X-ray microtomography is used to nondestructively section printed wiring boards in which conductive anodic filaments (CAFs) had grown, Quantification of the spatial distribution of copper is compared for microtomography and for serial sections obtained in SEM with backscattered electrons. The agreement between the techniques is excellent and indicates that microtomography may be used confidently to follow the subsurface growth of CAFs.

Considerable mechanical and environmental reliability testing as defined by MIL-STD-883 has been performed on GE HDI modules in both hermetic and nonhermetic configurations. The tests involving temperature cycling, temperature bakes, thermal shock, power cycling by self-heating, vibration, centrifuge and drop shock showed no change in the overlay or in the performance of the underlaying chips on the substrate. As an additional reliability test, the effect of humidity cycling (45° - 95° relative humidity) on nonhermetic HDI substrates has been also investigated. Any noticeable failures and degradation of metallization were not observed by humidity cycling itself at room temperature. Both the 883 and humidity cycling test could lead to the conclusion that HDI is a robust MCM-D technology. In addition, extensive studies on the residual stress analysis of the thin film layers of metal and polymer during fabrication and thermal cycling have been performed using the Flexus laser beam bending instrument. The study results predicted that failure of overlay HDI such as delamination between layers is less likely because of lower in-plane stresses than in conventional spin-coated and cured polyimide.

Microstructural differences in copper deposited by four techniques commonly used in the microelectronics industry were previously reported. [1] The reaction rates were predicted using either grain size or grain orientation as the dominant microstructure characteristic. A practical method to monitor copper speciation was developed.[2] This technique was used to measure the reaction rates for the different copper films under two different etching conditions. The results are explained using grain size, grain orientation and near surface region composition.

The use of gravure offset printing to transfer film patterns from an inked plate to the substrate by a silicone rubber pad has been shown to have promising advantages in fine line and multilayer production. The technology is now moving into the field of electronics manufacturing. By optimising the printing parameters and ink characteristics in the gravure offset technique, lines and spaces as narrow as 50 μtm were achieved and even finer lines are possible. Commercially available fine line thick film Au and Ag pastes were modified for this purpose. The thickness of sintered conductors ranged from about 2 to 11 μtm depending on ink viscosity, control of printing equipment and repetition of prints. When compared with films deposited by conventional thick film technology, the conductivity and adhesion on alumina were similr. The small interconnections between conductors through the insulator layer necessary in multilayer techniques were realised using gravure offset printing to coat excimer laser drilled vias. Interconnection diameters of less than 100 μtm were achieved.

We have developed a simple, compact and economical diode laser-assisted process for the direct writing of gold and copper on polyimide. Gold precursor films were deposited by spin-coating a commercially available organometallic compound onto the substrate. The local pyrolysis of these films was induced by the focused beam of an AlGaAs diode laser array ( Pmax = 1 W, λ = 796 nm). Direct writing was achieved in open air while moving the substrate at speeds up to 15 mm/s. Gold lines 13–17 μm wide, ∼0.1 μm thick, and having a resistivity of 30 μΩ·cm, were obtained on polyimide with good reproducibility using writing speeds > 10 mm/s. Following a simple annealing process, these gold lines successfully activated the electroless plating of copper. After 45 min of plating, 2 μm thick Cu/Au conductors, having a resistivity of 8 μΩ·cm, were deposited. A commercially available copper precursor was also studied for the direct deposition of copper.

We have developed a new two-step process to generate a metallic pattern on dielectric materials. This method employs ultraviolet (uv) laser irradiation followed by electroless deposition. A few laser pulses are required to generate the pattern. After immersion in an electroless bath, the metal film is deposited only on the uv exposed area. Results of the application of this method to aluminum nitride and alumina are presented. The laser irradiation step is very fast, and the electroless deposition is simplified because it does not require any special seeding to promote activation, i.e. laser irradiation activates the dielectric surface for electroless deposition. In addition, the laser-induced activation of the insulator is maintained for a very long time allowing electroless deposition to be performed many months after irradiation. Patterns in the tens of microns can be produced on laser-exposed substrates. Pull tests have been performed to determine the bond strength. We have found that the bond strength can be further increased by annealing.

Both electrodeposited and electroless copper are widely used in the electronics industry to form signal lines and plated-through holes in printed circuit cards and boards. Because of widely differing thermal expansion coefficients of copper and of the ceramic and polymeric substrates, large mechanical stresses develop in the metallization during thermal cycles, as e.g. during solder reflow. To safeguard against premature fracture it is imperative that the metallization is sufficiently ductile. Plated thin foil copper of poor ductility is known to be susceptible to cracks in plated-through holes which, besides causing problems in the manufacture, poses a threat to device reliability in service. In this paper we show that such cracks arise as a combination of reduced ductility due to presence of initial porosity in copper and due to grain boundary sliding and diffusional cavity growth during the soldering cycle. We emphasize that there exists strong interactions between these ductility reducing effects, such that their coupled action may exceed the effect when each mechanism operates independently. We review recent research on deformation and fracture of bulk and plated copper between RT and 300°C. Finally, we briefly discuss approaches to improve mechanical properties of plated thin foil copper.

A study was undertaken to select a suitable coating for a high-pin-count flexible edge connector (Flex) that interconnected a multichip thin-film silicon carrier to a printed circuit board. The Flex with cantilevered inner leads were joined to the contact pads at the perimeter of the carrier. 15 polymeric coatings were evaluated by subjecting coated Flexes to tests consisting of inner lead bending, temperature/humidity/bias (85°C/80%/15 V/350 hours), corrosion, line peel, and/or pressure cooker (126°C/20 psig/120 hours). Inner lead bending measurements were performed to assess the potential of lead shorting at the inner lead bonding sites during thermal cycling. From this study, a low-stress silicone evolved as the best candidate. The results leading to this conclusion will be shown and discussed.

Metal/ceramic bilayers fracture by one of three failure modes; crazing, spalling or interfacial failure. Models for these failure modes are developed. The results are presented as maps that can be used in the design and failure analysis of electronic packages. Examples are presented for several material systems, including A1N.

The microstructure of 95Pb-5Sn flip-chip solder bonds deposited on Cr/Cu/Au metallisation pads has been studied using both light and electron analysis techniques. The presence of Sn-Cu- Au ternary intermetallic phases was detected within the Pb-rich matrix at significant distances from the originally deposited interface. The distribution of the phases present after the solder has undergone a reflow heat treatment can be interpreted using recent equilibrium ternary diagram data. An investigation was also made into the effects of various non-reflow heat treatments at carefully chosen temperatures, to qualitatively evaluate the extent of solid state diffusion and the resultant phase distribution.

One of the important way to improve the property of solder joints is to improve the property of solders, This paper is about a study of Sn-Pb-RE solder(RE-Rear Earth, mainly contains Ce and La). It has been shown that the final form of RE in SnPb60/40 solder is Sn-RE intermetallic compound, and a very little RE can change the solder microstructure greatly. The influence of RE on solder life of creep rupture is that Sn-Pn-RE solder has much long life than that of SnPb60/40, and the solder life increases with the increase of RE content.

For a number of years electronic manufacturers of printed circuit assemblies have used rosin-based soldering fluxes. Post-solder cleaning was accomplished with chlorinated or chlorofluorocarbon (CFC) solvents. With the elimination of these solvent options due to their destructive effect on the stratospheric ozone layer, manufacturers are looking to alternative cleaners for rosin flux or to new flux choices which can be cleaned with water, or left uncleaned.

Many of the flux formulations are new and their long-term effect on the performance of product manufactured with them is unknown. Although ionic contamination testers can alert one to the ionic levels remaining on an assembly, the corrosivity of the residues is not directly related to the total ionic level, but only to certain ionic species. Surface insulation resistance testing is used by many in the industry, but the results are complex and often misunderstood.

All of these factors have been the driving force to develop a quantitative screening test for soldering flux residues. This test, originally conceived by Dr. David Bono, has been modified and developed at Georgia Tech to provide a quantitative evaluation of flux residue corrosivity. This work, in collaboration with the work being performed by the French standards group, will result in a new international industry standard. This paper reports the latest data on this important test development.

Thermal cyclic shear stress/strain hysteresis response of 97Sn-2Cu-0.8Sb-0.2Ag, 95.5Sn-4Cu-0.5Ag, 63Sn-37Pb, and 62Sn-36Pb-2Ag solder joints have been determined using a double beam specimen. The temperature cycle had a period of 40 minutes and extreme temperatures of 40°C and 140°C.The steady state creep properties of these solders were determined, and the associated Norton's law was implemented in a finite element program to simulate the experiment. The fatigue life of these solders joints and failure mechanism are also discussed.

This study was conducted in order to determine and understand the effect of substrate on eutectic In-Sn. Samples for mechanical testing were produced with either bare Cu or Ni on Cu substrates. Both the microstructure and the mechanical behavior are strongly dependent on substrate, with In-Sn on Cu having a non-uniform and irregular microstructure and In-Sn on Ni having a uniform, normal colony-based eutectic. Deformation is more uniform in the In-Sn on Ni, while it is concentrated along the length of the joint in the In-Sn on Cu. This is reflected in the different shapes of stress-strain curves between In-Sn on Cu and In-Sn on Ni. The stress exponents and activation energies for creep also vary with substrate. Creep deformation is governed by the In-rich γ phase for In-Sn on Cu and by the Sn-rich y phase for In-Sn on Ni. If In-Sn on Ni samples are aged, the microstructure coarsens and the mechanical behavior changes to resemble that of the as-cast In-Sn on Cu.