In designing a complex circuit, designers make a large number of circuit simulations, design changes and optimizations and can predict the circuit's performance reasonably accurately before committing it to silicon. It would be unthinkable to bypass detailed circuit simulation and optimization and rely on simple design rules and the testing of finished IC's to discover errors or to find out if the performance of the circuit meet specifications. Yet, this is basically the way IC reliability is treated today. A logical alternative is to predict circuit reliability at the circuit design stage through reliability simulation.

Reliability simulator BERT is used to illustrate the physical models and approaches used to simulate the hot electron effect, oxide time-dependent breakdown, electromigration, bipolar transistor gain degradation, and radiation effects. The goal is to make circuit reliability simulation a part of the IC design process.

In this paper hot carrier related aging of n-p-n bipolar transistors is investigated experimentally and theoretically to bring physical insight into the bipolar transistor hFE (common emitter current gain) degradation. Electrical stress experiments are performed on transistors with different base doping profiles at varying temperatures. Detailed process simulations are performed to determine the doping profiles of the base-emitter junction. Monte Carlo transport simulations are then performed at different temperatures and bias conditions to determine the electron and hole distribution functions in the baseemitter junction. AT&T's 0.8 μ.m BICMOS technology is used to fabricate the experimental bipolar transistor structures. For this non-self aligned technology we attribute hFE degradation to the presence of hot holes and secondary electrons which are generated by hot hole impact ionization. This feed-back due to impact ionization has a dominant effect on the high energy tails of the distribution of both holes and electrons even when the overall current multiplication is low. Simple hot electron energy transport models do not contain the complexity to properly describe ionization feedback and carrier heating, and are therefore inadequate. An exponential dependence of the transistor lifetime on BVEBO is deduced for constant voltage stress (Vstress < BVEBO) conditions, confirming the importance of secondaries in the process of degradation.

This paper describes an application of process and device simulation programs in the study of substrate current generated by hot-carrier effect in submicron p-channel MOSFET devices. The impact ionization model for holes was calibrated for accurate simulation of substrate current in submicron devices, and an expression for the impact ionization rate of holes in silicon is obtained. The simulated substrate current for 0.57, 0.73 and 1.13 μm devices obtained by the optimized expression agrees very well with the measured data. The optimized impact ionization expression was also used to simulate the effect of p- Lightly Doped Drain impurity profile on substrate current, and the simulated peak substrate current and the corresponding maximum lateral channel electric field as a function of p- dose and length are presented.

The behavior of small MOS structures with polycrystalline silicon gates subjected to stresses caused by electron injection was analyzed. A nature of degradation in MOS structures is more clearly and reliably extracted from the investigations of the microstructures with active areas less than 10 μm2. NVM cells with floating gate are convenient objects for such investigations. Due to the high current sensitivity and range of described novel techniques (10-17 - 10-7 A), small tunnel oxide area in memory cell (1-5 μm2) and temperature measurements (120 - 438 K) some new results in oxide degradation have been found.

In this work the following chain of degradation processes during electron injection was experimentally detected: conversion from planar to local injection (area of localization~10-3 um2) => appearance of percolated path for low field leakage (it is defined by sufficient amount of generated deep level traps in dielectric Nt~ 1020 cm-3) => development of leakage channel into the breakdown region. TDDB method usually developed on large MOS structures with electrostatic energy more than critical value 107 eV is not able to distinguish this chain and correctly evaluate degradation. Taking into account a localization of electron injection, it was found that the charge to the leakage channel generation is about 104 -105 Cl/cm2 for cells without fabrication defects. A kinetics of localization is very sensitive to the tunnel oxidation process.

Degradation stages of NVM cells, subjected to different electric stresses and anneals, have been investigated in wide current and temperature ranges. Polaron and Trap Model for the I-V leakage characteristics of degraded SiO2 films is presented.

Projections on density, performance and cost attributes of a new technology generation are relatively easy to accomplish. However, defining the reliability attributes is more problematic, particularly if the technology contains many new process elements or tools. The choices made by a development team for processes, tools, process sequences and product-layout rules often determine the process defect reliability fail modes of a technology. These process defects define the reliability level of products rather than classic reliability fail mechanisms such as electromigration, stress migration and corrosion. As such, development teams and their reliability counterparts need to focus on potential sources of process-defect reliability fail modes and their control.

In a Mixed-Signal IC, both digital and analog circuits exist on the same chip. Analog circuit blocks require technology attributes like precise device matching, low parametric drifts and low noise. These requirements raise additional reliability issues, over and above the reliability concerns associated with digital circuits. CMOS device reliability for mixed-signal technologies can be enhanced by modifying device architecture and improving gate oxide integrity. Interconnect metallurgy plays an important role in determining electromigration related contact/via resistance change which may impact matching of devices and resistor pairs. Appropriate source/drain engineering, device design and utilizing nitrided gate oxide has been shown to produce extremely stable devices. This article will cover process architecture and material issues related with device stability and interconnect metallurgy issues related with contact/via stability, especially with W-Plugs.

Because of its high thermal conductivity, free-standing CVD-diamond is an extremely attractive material for application as the substrate in multichip modules (MCMs). However, this material does present some technological challenges, one being the development of reliable metallization systems. In this work, adherent metallization systems, such as Au/Ti, Au/Ti-W, Au/Ni-Cr, Au/Cr and Cu/Cr have been produced at low temperatures. Thin adhesion/seed metal layers were deposited using sputtering and evaporation techniques. Gold and copper metallization of several microns thickness was accomplished by electroplating over the thin metal layer. Post-deposition annealing of both the adhesion/seed layer and plated metallization systems were performed at temperatures up to 500°C in an effort to enhance adhesion and determine the impact of subsequent high temperature operations on reliability issues such as intermetallic diffusion, delamination, and the impact of surface microcavities. Extremely adherent Au/Cr and Cu/Cr metallization systems appropriate for use in MCM technology were developed.

While hillocks usually form to relieve compressive stresses in thin films resulting from electromigration or a difference in thermal expansion in the film and substrate, we have observed hillock formation in tensile-loaded films. We have used transmission electron microscopy to study hillocks which formed in free-standing gold thin films of 25nm nominal thickness. Grain growth during 150°C anneals reduced the grain boundary area and associated free volume, placing the films under tensile stress. While hillock formation could only increase this stress, large single crystal or polycrystalline hillocks with thicknesses up to three times the film thickness are observed after 400°C annealing, after long room temperature anneals, and during TEM observation. These observations suggest the operation of a hillock formation mechanism not explained by any existing hillock formation theories.

The stresses in single crystal and polycrystalline Al films were determined by wafer curvature measurements during temperature cycling. Both elastic and plastic behavior was observed. The single crystal film exhibited anisotropic yield stresses indicating that dislocation glide is the dominant deformation mechanism. The polycrystalline film exhibited similar behavior, although without the anisotropy, indicating that it too deforms by dislocation glide. Unlike the single crystal film, the yield stress in the polycrystalline film varied depending on thermal and deformation history. These effects are attributed to the presence of grains and grain boundaries in the polycrystalline film.

Multilayered thin films were deposited on pure Al substrate test bars for in situ scanning electron microscope (SEM) microtensile deformation. The films consisted of a TiN layer covered by either SiO2 or W. Deformation of the samples showed that the TiN film dominated cracking events and caused cracking in the W to occur at lower critical stress values than previously reported. Crack deflections along the TiN-W interface were also seen. W film strain was measured by X-ray diffraction before and after testing to look at the effect of cracking and deformation on stress in this film.

Interfacial debonding of multi-layer thin film systems can severely affect the reliability of devices. To quantitatively evaluate the interface adhesion strength, a sandwich structure four-point bending technique was developed. In the sandwich structure samples, the thin film structure of interest was diffusion bonded between two silicon substrates. A fourpoint bending method was applied to propagate a crack along the interface of interest. Two thin film systems with nominally the same structure, but processed under different conditions, were measured for their SiO2/TiN interface fracture energies. Results showed that the interface fracture energy of one system was about 50% larger than that of the other system. Cross-section TEM observations revealed that the stronger interface was also significantly rougher.

Differences in strain energy density between grains of different orientation within a thin film may drive morphological changes such as abnormal grain growth, hillocking, and sunken grains. Models of these morphological changes generally assume that the behavior of each grain is the same as that of a blanket film of corresponding orientation. In order to investigate this assumption as it applies to the behavior of a (100)-oriented grain within a {111}-fiber textured copper film, simple continuum analytical and finite element models are applied to the case of a film on a rigid substrate subjected to temperature changes. The simple models indicate that the behavior of a misoriented grain does not simply duplicate that of a blanket film of the same orientation; the behavior of the surrounding grains must also be considered. The strain energy density difference between the grain and the surrounding film is less than that predicted by blanket film behavior. An elasticity equation is presented which describes the average stress-temperature behavior of widely dispersed misoriented grains within a textured film.

Sputtered Cu films on Si, Al and Cu substrates were thermally cycled to 300 °C at a rate of 6 °/min, which induced an applied thermal strain that was compressive, tensile and zero, respectively. Microstructural characterization of the annealed films revealed abnormal (100) grain growth in the films on Al and Si, but not Cu substrates. In addition, symmetric x-ray diffraction scans demonstrated that the films in which abnormal grain growth was observed were primarily (100) in orientation. In contrast, the Cu film on a Cu substrate was largely randomly oriented after cycling, with a small degree of (111) preferred orientation. These results are consistent with a strain energy driving force for abnormal grain growth, which predicts that the growth should occur in compression, as on the Si substrate, or in tension, as on the Al substrate, but not when there is no applied thermal strain, as on the Cu substrate.

Micro-Raman spectroscopy, XRD, and analytical modelling are used to study stresses in and surrounding tungsten lines of different widths and spacing. The stress in the lines and in the adjacent substrate is calculated using a concentrated- and a distributed edge force model. Both models are adapted such that the substrate-stress components can also be calculated for an array of lines. The results from XRD and micro-Raman spectroscopy and the results from the distributed edge force model are in agreement. The combination of data from the two experimental techniques is shown to give some important feed-back to the theoretical models.

We have studied stress states in chemical vapor deposited (CVD) tungsten (W) for both blanket films and lines, to understand better the mechanical implications of intrinsic stress for interconnection structures. Since W has a low mobility at its deposition temperature, a very large intrinsic stress develops during deposition. Intrinsic strains in blanket W films were measured with an X-ray technique. The measured strains correspond to a biaxial tensile stress of the order of 1 GPa. This result was used to provide an initial strain input in a finite element calculation to obtain intrinsic stress states in W lines. SEM observation of cross sections of the metal lines enabled us to determine the growth pattern of the W, and infer the boundary conditions during growth. Finite Element Method (FEM) calculations of the room temperature stress in the lines, including both intrinsic and thermal components, are in good agreement with X-ray determinations.

Time-Dependent Dielectric Breakdown studies were performed on 6.5-, 9-, 15-, 20-, and 22.5-nm thick SiO2 films over a wide range of stress temperatures and electric fields. Very high temperatures (400 °C) were used to accelerate breakdown so that stress tests could be performed at low electric fields close to those used for device operating conditions. The results indicate that the dependence of TDDB on electric field and temperature is different from that reported in earlier studies. Specifically, the electric-field-acceleration parameter is independent of temperature and the thermal activation energy was determined to be between 0.7 and 0.9 eV for stress fields below 7.0 MV/cm.

Failure distributions of high-quality current-generation oxide films are shown to be of single mode and have dispersions that are not sensitive to stress electric field or temperature, unlike distributions observed for oxides examined in earlier studies. These results have implications on the choice of the correct physical model to describe TDDB in thin films. The data also demonstrate for the first time the reliability of silicon dioxide films at very high temperatures.

Effect of Fowler-Nordheim current stress on (100) p-Si metal/oxide/semiconductor diodes have been studied by means of a.c. conductance measurement. Growth of two distinct peaks are observed in the depletion and the inversion resions corresponding to the generation of two kinds of defects in the upper and lower halves of the bandgap. These defects show different behaviors against the current stress in the energy profiles of the density and the capture cross section. The degradation of the Si/SiO2 interface is discussed in relation to the defect creation.

The effect of electric arc plasma jet treatment (APJT) on MOS structure reliability has been investigated. Si/SiO2/Si*/Al structures have been studied using the technique of constant current charge to breakdown before and after APJT. The study showed that APJT can improve MOS structure reliability: constant current charge to breakdown Qbd increased to more than 5 C·cm-2 and breakdown field Ebd increased to more than 20 MV/cm. This result was attributed to a structural modification of SiO2 and its interfaces as a result of APJT. Evidence for these structural changes is the appearance of additional SiO2 IR absorption peak which was observed by us.

The effects of electron cyclotron resonance (ECR) N2O-plasma nitridation on the characteristics of thermal SiO2 have been investigated. Although the ECR N2O-plasma nitridation was performed at low-temperature(≤400°C), it was found that oxynitride layer can be successfully grown at the Si/SiO2 interface. The atomic concentration of nitrogen near the Si/SiO2 interface was comparable to that of high temperature N2O annealing. The ECR N2O-plasma nitrided thermal SiO2 exhibits higher breakdown field characteristics, higher time-to-breakdown and charge-to-breakdown values in comparison with those of thermal SiO2. In addition, ECR N2O-plasma nitrided thermal SiO2 shows improved charge trapping properties

Microstructure evolution in polycrystalline metallic thin films under stress and electric current underlies many reliability issues in microelectronics. This paper presents a quantitative analysis of grain-boundary and void dynamics based on the coupling between bulk and interfacial mass transport phenomena with elastic deformations and current stressing. The formation and growth of intergranular voids in bamboo-structure conductor lines due to stresses that develop during processing is analyzed. The analysis is aided by self-consistent simulation of bulk and grain-boundary diffusional processes using bicrystal models with elastic grains. A systematic analysis is presented of the morphological evolution of transgranular voids in aluminum lines under current densities that are typical of electromigration testing. The effects of the electric field and surface properties on the morphological stability of voids are examined and morphologies that bifurcate from rounded or wedge-like void shapes are predicted. The theoretical results are discussed in the context of experimental data for void propagation under electromigration conditions.