A 63nm Twin Flash memory cell with a size of 0.0225μm2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.

Electrical bistability is reported in metal-organic-metal diodes. The device consists of two Al electrodes separated by an organic layer that contains embedded Au nanoparticles (NPs) supported by parylene nanopillars. This paper presents results with two different organic materials: 2-amino-4, 5-imidazoledicarbonitrile (AIDCN) and aluminum tris(8-hydroxyquinoline) (Alq3). Electrical characterization of the diodes shows bistability with two well-defined states with high (OFF) and low (ON) resistances. The ON/OFF ratio is 104 and current-voltage (I-V) curves show a negative differential resistance (NDR). The diodes can be programmed in either the ON or the OFF state and maintained it for at least 8 months in air without any evidence of degradation. This conspicuous memory effect is rationalized in terms of charge storage mediated by the oxidation/reduction of the NPs. The fabrication method is general and provides a good control on both the size-uniformity and the position of the Au NPs embedded in the organic materials. The diode characteristics with different NP density are also addressed.

SiOx (x<2) films were deposited in an O2 atmosphere using Si target in a pulsed laser deposition system. Post-annealing process was employed in an O2 atmosphere to form the nanometer-sized Si crystallites embedded in the SiO2 films. The transmission electron microscope analysis shows the existence of crystalline silicon nano-dots with diameters ranging from 2 to 4 nm. Also, the clear separation of Si and SiO2 phases can be seen in the X-ray photoemission spectra. Photoluminescence peak from the annealed films was obtained, which is attributed to the quantum confinement effect of the Si nano-dots. C-V measurements of the metal-oxide-silicon (MOS) structure containing the silicon nano-dots in the oxide layer were performed to investigate the charging/discharging behavior of the silicon nano-dots. The maximum program window of the MOS was measured to be4.1V under ±5V sweep.

Organic based electronic memory devices are currently receiving an unprecedented amount attention as possible alternatives for conventional semiconductor memories, due to their simple device structures, ease of fabrication, compatibility with flexible substrates and low cost. Polymer memory devices (PMDs) based on active layers containing gold nanoparticles (Q-Au) with 8-hydroxyquinoline (8HQ) will be presented in this report. Memory performance attributes will also be presented, which are less reported in the literature, but still essential for the realisation of viable organic memory technologies.

In this paper, ferroelectric materials suitable for realizing high-density 1T1C-type (capacitor-type) FeRAM are first reviewed. It is found in BiFeO3(BFO) films formed by chemical solution deposition that leakage current density at a low electric field increases by substitution of Mn and Cr atoms for Fe atoms. But, it is also found that the breakdown characteristic is much improved by substitution of these atoms. Because of the better breakdown characteristic, the leakage current densities in the 3 and 5% Mn-substituted films are lower than that in an undoped BFO film at an applied electric field of 1MV/cm at room temperature, and thus well saturated hysteresis loops in P-E (polarization vs. electric field) characteristics are observed in these films.

Next, recent technological progress in transistor-type FeRAM, in which data are stored in a single ferroelectric-gate FET(field effect transistor), is discussed. It is demonstrated that the data retention time of ferroelectric-gate FETs is much improved by use of HfO2-based buffer layers which are inserted between the ferroelectric film and Si substrate for preventing interdiffusion of constituent elements. Particular attention is paid to FETs with a Pt/SrBi2Ta2O9/HfO2/Si gate structure, in which the data retention time longer than 30 days has been attained. Finally, the cell structure and operation principle of 1T (one transistor)-type FeRAM are discussed.

Electric-pulse induced resistance (EPIR) change effect encompasses the reversible change of resistance of a thin oxide film under the application of short, low voltage pulses. The phenomenon is widely observed in complex and binary oxides, and is the basis for development of non-volatile resistance random access memory (RRAM). A variety of analytical techniques have been employed to understand the origin of the resistance change with recent data yielding a model incorporating oxygen ion/vacancy diffusion and pile-up near the interface region of the oxide at the impervious metal interface. Further efforts are still required to fine tune the model and apply it to the optimization of RRAM device development.

The nonlinear absorption coefficient of As2S3 glass has been measured to be 2.0 cm/GW for femtosecond pulses at 800 nm. Femtosecond laser structuring via two photon absorption in bulk As2S3 glass by erasable and permanent photo-darkening is demonstrated using both holographic and direct multi-beam laser writing.

This work describes a novel nonvolatile memory device with self-aligned TiSi2/Si hetero-nanocrystal charge storage nodes. The TiSi2/Si hetero-nanocrystals can be readily fabricated using industrial standard self-aligned silicidation technique based on Si nanocrystals deposited on ultra-thin tunnel oxide with LPCVD. As compared with a Si nanocrystal memory device, a TiSi2/Si hetero-nanocrystal memory device exhibits faster programming and erasing, and longer retention time.

A large negative resistance is observed in the I-V characteristics of gold nanogap junction when high-bias voltages are applied. This phenomenon is characteristic behaviour on the nanometre scale; it only occurs for gap widths slightly under 13 nm. Furthermore, this junction exhibits a non-volatile resistance hysteresis when the bias voltage is reduced very rapidly from a high level to around 0 V, and when the bias voltage is reduced slowly. This non-volatile resistance change occurs as a result of changes in the gap width between the metal electrodes, brought about by the applied bias voltage.

In this work, we report on the synthesis and characterization of thin films of (BiFeO3)1−x (PbTiO3)x (BFPT) solid solutions of compositions around morphotropic phase boundary (MPB) grown on platinized silicon (111) Pt/TiO2/SiO2/Si substrate by sol-gel based spin coating technique. The films were post-annealed at 700 and 750°C for 1 h in air. Morphological analysis of the films was carried out by scanning electron microscopy. Grazing incidence X-ray diffractometry revealed the perovskite structure of the films and peaks suggested the presence of rhombohedral structured pure BFPT phase in polycrystalline form. Scanning electron microscopy suggested that films annealed at 750degC had a denser microstructure as compared to those at 700°C. The room temperature dielectric constant of the films with composition of BF:PT :: 75:25 was measured to be ∼1200 at a frequency of 100 kHz.

We report the synthesis of GeTe, Sb2Te3 and Ge2Sb2Te5 nanowires via a gold-catalyzed vapor-liquid-solid mechanism. The nanowires are studied via electron microscopy and energy-dispersive X-ray spectrometry and are found to be single crystalline. For electrical measurements contact to individual nanowires is made via electron-beam lithography. The nanowires can be switched from their initially low resistance state to a higher resistance state by applying a 200ns voltage pulse. Switching back to the low resistance state is possible via annealing. Electric force microscopy studies show the switching takes place at the metal-nanowire contact.

Chalcogenide Random Access Memory (C-RAM) has shown significant promise in combining the desired attributes of an ideal memory, including: nonvolatility, fast read/write/erase speed, low read/write/erase voltage/power, high endurance, and radiation hardness. Current C-RAM production technology relies on sputtering to deposit the active chalcogenide layer. The sputtering process leads to difficulties in meeting requirements for device conformality (in particular – filling vias), film adherence, compositional control, wafer yield, and surface damage. Ultimately, a viable CVD manufacturing process is needed for high-density products to realize the full potential of C-RAM. In this work, we discuss the Metal-Organic Chemical Vapor Deposition (MOCVD) tool technology used to produce the films and report the materials properties of GeSbTe-based chalcogenide thin films grown in small research scale and in large production scale MOCVD reactors. Films were grown at low pressures at temperatures ranging from 350 C to 600 C. X-Ray Fluorescence (XRF) and Auger Electron Spectroscopy (AES) were performed and determined that the film composition is controllable and uniform.

A study of electric-pulse-induced crystallization of Ge2Sb2Te5 (GST) was conducted by in situ scanning electron microscopy observation and resistance measurement. A lateral phase-change memory with a top GST channel connected by two separate underlying electrodes was adopted in this study to easily observe the crystallization process. At a low voltage pulse, randomly distributed nuclei were initiated. At the first growth stage, these nuclei grew fast with the pulse amplitude at a rate of around 60 nm/V and then growth rate slowed down to around 14 nm/V when the grain diameter was closed to film thickness. Device resistance during crystallization dropped by around one order of magnitude, which should be due to amorphous to face-centered-cubic transition.

Indium tin oxide (ITO)-channel ferroelectric-gate thin film transistor (TFT) with large on/off current ratio is demonstrated by using mechanical polishing process to planarize the surface of ferroelectric bottom gate insulator (Bi,La)4Ti3O12 (BLT). It is shown that the mechanical polishing of the sol-gel derived polycrystalline ferroelectric BLT films causes no degradation in electrical properties. ITO channel layer was then deposited on the planarized BLT gate insulator to fabricate ferroelectric-gate TFTs. The off-current of the ITO/BLT TFT fabricated with the polishing process is drastically reduced to around 10−12 A, which is four orders of magnitude lower than that of the TFT fabricated without the polishing process. The obtained on/off current ratio is more than 107. In addition, a subthreshold voltage swing as small as 200 mV/decade was obtained.

Reversible structural phase change phenomenon of certain chalcogenide materials has been investigated extensively in the past decades. Among various phase change chalcogenide materials, Ge2Sb2Te5 (GST) is the most studied material due to its superior optical, electrical and mechanical properties. One of the challenges in using GST is the poor adhesion between crystalline GeSbTe (c-GST) and the substrate, such as TiN. In this work, the adhesion of the c-GST/TiN interface of two samples deposited by different techniques was characterized using four-point bend, nanoindentation and nanoscratch techniques. The nanoindentation and nanoscratch data agree well with the four point bend data. The paper also discusses the application potential of nanoindentation and nanoscratch techniques as qualitative methods for adhesion evaluation in semiconductor process development.

With the help of the high resolution Z-contrast scanning transmission electron microscopy (STEM), the near edge fine structures of the electron loss spectroscopy (EELS) arises from different layers are investigated in SBT. The EELS spectra are interpreted by comparing with the calculation using linearnized augment plane wave (LAPW) method within the local density approximation (LDA). The oxygen bonding nature in different layers are discussed. In Bi2O2 layer, oxygen 2p state interacted with the Bi 6p state leads to a high t2g state in density of state while in SrTa2O7 layer, oxygen 2p state hybridized with Ta 5d and Sr 5d, which leads a higher eg state than t2g state.

Magnetron sputter deposition of Ge2Sb2Te5 film is presented. Good thermal control of the wafer is found critical for maintaining process repeatability. In-situ wafer heating conditions have strong impact on as-deposited Ge2Sb2Te5 film properties such as resistivity, density, stress, composition, and microstructure. The effects of wafer bias and sputtering pressure are also discussed.

In this work, the charge-trapping distributions of polysilicon-oxide-nitride-oxide-silicon (SONOS) structure are studied. The trapping energy level of SiNx films with different composition ratio deposited by low-pressure chemical vapor deposition (LPCVD) were first characterized by photoluminescence (PL) measurement. Moreover, using F-N/CHE program and charge pumping techniques, the vertical location and the lateral distribution of programmed charges are investigated in the nitride films with different composition ratio. The study offers strong evidence that the density of charge-trapping levels in the Si-rich nitride is higher than the standard nitride. A simple qualitative model and calculation explains that the trapping level distributions in the SiNx films are shallower by increasing relative Si-content. Furthermore, we have observed the nitride trap vertical location was changed by adjusted Si/N composition ratio. And the lateral distribution of hot electron programmed charges in the modified nitride is broader than that in the standard nitride because it offered more charge-trapping sites and shallower charge-trapping levels. In summary, the study can help researchers to understand the nitride charge-trapping mechanism and the analysis of optical/electrical characteristics.

A ferroelectric crystal with perovskite structure such as PbZr1−xTixO3 (PZT), SrBi2Ta2O9 (SBT), Bi3La1−xTixO12 (BLT) and non-perovskite structure such as Pb3Ge5O11 (PGO) have two polarization states, which can generate two resistance states: high resistance and low resistance states. These properties can be used for resistance random access memory applications (RRAM). When a ferroelectric capacitor is polarized an internal electric field opposite polarity to the external applied field is generated. As a result there is a large resistance change at a given bias voltage between the two polarization states of the capacitor. It is the purpose of this paper to show that the ferroelectric capacitor may be used as a current memory cell of non-destructive readout (NDRO) non-volatile Random Access Memory array. It will also be shown that each current sensing ferroelectric memory cell stores two bits of memory information and exhibits long memory retention and excellent endurance properties.

This work reports on the formation of Si-nanocrystals within silicon nitride layers by low-energy Si ion implantation. Electrical characterization of oxide/Si-nanocrystal-nitride/oxide dielectric stacks demonstrates regions of negative differential resistance at low-fields. In addition, the memory characteristics in terms of charge trapping, write/erase response and retention properties of the dielectric stacks were recorded. The results indicate the large potential of the low-energy ion beam synthesis method in nitride memory technology.