In this report we present results comparing lateral MOSFET properties of devices fabricated on Si-face (0001) and A-face (11-20) 4H-SiC, with nitric oxide passivation anneals. We observe a field-effect mobility of 33 cm2/V.s on p-type 5×1015 doped Si-face. These devices have a peak field-effect mobility which increases with temperature, indicative of a channel mobility limited by coulomb scattering. On 1×1016 p-type A-face SiC, the peak channel mobility is observed to be 80 cm2/V.s, with a negative temperature dependence, indicating that phonon-scattering effects dominate, with a much lower density of shallow acceptor traps. This > 2x higher channel mobility would result in a substantial decrease in on-resistance, hence lower power losses, for 4H-SiC power MOSFETs with voltage ratings below 2 kV. However, MOS C-V and gate leakage measurements indicate very different oxide and interface quality on each SiC face. For example, the Fowler-Nordheim (FN) conduction-band (CB) barrier height for electron tunneling at the SiO2/SiC interface is 2.8 eV on Si-face SiC, while it is 2.5 eV or less on A-face SiC. For the valence-band side, the effective FN barrier height at the valence-band (VB) side of only 1.6 eV on A-face SiC, while the VB barrier height is about 3.1 eV on Si-face SiC. Moreover, C-V of the MOS gate on A-face indicates the presence of a high-density of deep hole traps. It is apparent that oxides on alternative crystal faces, very promising in terms of channel mobility, require further study for complete understanding and control of the interface properties.

Energetically-deposited carbon contacts to n-type 6H-SiC have exhibited either insulating, rectifying or ohmic electrical characteristics depending on the average energy of the depositing flux and the substrate temperature. Deposition at room temperature and at a low-medium average energy (<500 eV) has resulted in carbon with a low graphitic content and insulating electrical contacts. With higher average energy and at a moderately elevated temperature (∼100 °C), the higher graphitic content contacts were rectifying with an ideality factor, η, of ∼1.8 and barrier height of ∼0.88 eV. Oriented graphitic carbon deposited at 200 °C with biases exceeding 300 V formed ohmic contacts.

The correlation of stress in Silicon Carbide (SiC) crystal and frequency shift in micro- Raman spectroscopy was determined by an experimental method. We applied uniaxial stress to 4H- and 6H-SiC single crystal square bar specimen shaped with (0001) and (11-20) faces by four point bending test, under measuring the frequency shift in micro-Raman spectroscopy. The results revealed that the linearity coefficients between stress and Raman shift were -1.96 cm-1/GPa for FTO(2/4)E2 on 4H-SiC (0001) face, -2.08 cm-1/GPa for FTO(2/4)E2 on 4H-SiC (11-20) face and -2.70 cm-1/GPa for FTO(2/6)E2 on 6H-SiC (0001) face. Determination of these coefficients has made it possible to evaluate the residual stress in SiC crystal quantitatively by micro-Raman spectroscopy. We evaluated the residual stress in SiC substrate that was grown in our laboratory by utilizing the results obtained in this study. The result of estimation indicated that the SiC substrate with a diameter of 6 inch remained residual stress as low as ±15 MPa.

4H-SiC p+n photodiodes based on ultrathin-junctions have been fabricated with distinct processes for the p+-region creation: either with Aluminium conventional ion implantation, or with Boron Plasma Ion Immersion Implantation. Spectral sensitivity measurements were performed at several temperatures from room temperature up to 340°C, with incident wavelengths ranging from 200 to 400 nm. Both responses are characterized by a stability between 200 and 270 nm, and a important increase with temperature between 270 and 380 nm. This fact has to be related to the two different kinds of optical absorption phenomena in SiC with respect to the wavelength, which are direct and indirect (phonon assisted) transitions. When decreasing the temperature, we noticed a hysteresis effect, which could be due to charge trapping by temperature activated defects. After strong proton and electron irradiations, the diodes showed a stability of the response below 270 nm, making them suitable for use in harsh environments. Simulation was performed at room temperature, with a good correlation between simulated and experimental room temperature curves.

This paper discusses formation mechanisms and potential paths to reduce defect density in current SiC epitaxy technology. Comprehensive optimization efforts have resulted in defect density measured by laser light scattering below 0.5 cm-2 for 30 um thick epi wafers. Possible approaches to reduce basal plane dislocations and mitigate interfacial dislocations are discussed. The progress in epitaxy defect reduction has been made on the foundation of the high quality 100mm substrates. The average and median BPD density is 700 cm-2 and 500 cm-2, respectively, and a low TSD density is also achieved simultaneously with both average and median values around 350 cm-2. High quality and low stress 150mm substrates have been obtained with very low TSD density of <150 cm-2.

4H-SiC substrates were annealed at 1500 °C for 30 min in 0.01 MPa Ar gas flow to make a graphene film. To clarify the effect of Al ion implantation and pre-plasma treatment, the graphene was fabricated on four different kinds of SiC substrates: without plasma treatment, with plasma treatment, Al ion-implanted without plasma treatment and Al ion-implanted with plasma treatment. The graphene films were analyzed by AFM and Raman spectroscopy. The Al ion implanted sample, which was then processed by CF4 plasma, showed small surface roughness of 3.49 nm (RMS), while the sample without CF4 plasma treatment showed large surface roughness of 8.41nm. Similar results were also observed for SiC samples without Al ion implantation. In Raman spectra, strong D-band, G-band and 2D-band signals were detected on both ion-implanted samples after annealing at 1500 °C, but weak D-band were observed on both samples without Al ion implantation. Raman mapping (2D-FWHM) showed that the graphene on ion-implanted SiC treated with CF4 plasma was more homogeneous than the one without CF4 plasma treatment. Hall measurements for SiC without Al ion implantation showed that graphene on SiC treated with CF4 plasma has higher mobility (389 cm2/Vs) than that without plasma treatment (136 cm2/Vs). Additionally, p-type graphene can be fabricated on Al ion-implanted SiC by CF4 plasma treatment.

Semi-insulating (SI) silicon carbide (SiC) was evaluated as a candidate material for dielectric substrate for patch antennas suitable for monolithic antenna integration on a SiC semiconductor chip. Computer simulations of the return loss were conducted to design microstrip patch antennas operating at 10 GHz. The antennas were fabricated using SI 4H-SiC substrates, with Ti-Pt-Au stacks for ground planes and patches. A good agreement between the experimental results and simulation was obtained. The radiation performance of the designed SiC based patch antennas was as good as that normally achieved from antennas fabricated using conventional RF materials such as FR4 and Rogers. The antennas had the gain around 2 dBi at 10 GHz, which is consistent with the conventional antennas of a similar size.

SiC power devices can handle large power and high frequency switching beyond the Si power devices. Typical full-SiC power modules are composed of both SiC-MOSFETs and SiC-SBDs to suppress the degradation of Ron of SiC-MOSFET during the bipolar reverse-current flow while there will be unfavorable consequences such as increased material cost, larger area, and larger wiring inductances. Panasonic has proposed the SiC-DioMOS which successfully integrates the unipolar reverse diode without any increase of chip size from the original DIMOS transistor. The SiC-DioMOS utilizes the highly-doped n-type epitaxial channel under the MOS gate for the FET channel and also for the reverse conduction path of the diode. Thickness and concentration of the highly-doped n-typed channel are carefully designed to achieve reasonable Vth of the MOSFET and Vf0 barrier constituting the diode current. The MOSFET and also the MOS-channel diode completely operate under unipolar mode. The SiC-DioMOS with BVds=1700V, Ron=20mΩ、Vth=4.5V, Vf0=0.8V is successively fabricated using the state-of-the-art epitaxial-growth technique. Fast switching of tr=58ns and tf=13ns is confirmed. The SiC-DioMOS meets practical standards for safety operation of high-power fast switching without SiC-SBD.

In this paper, high temperature (>1400°C) thermal oxidation has been applied, for the first time, to 4H-SiC PiN diodes with thick (110 μm) drift regions, for the purpose of increasing the carrier lifetime in the semiconductor. PiN diodes were fabricated using 4H-SiC material that had undergone thermal oxidation performed at 1400°C, 1500°C and 1600°C, then were electrically characterized. Forward current-voltage (I-V) measurements showed that thermally oxidized PiN diodes exhibited considerably improved electrical characteristics, with devices oxidized at 1500°C having a forward voltage drop (VF) of 4.15 V and a differential on-resistance (Ron,diff) of 8.9 mΩ-cm2 at 100 A/cm2 and 25°C. Compared to typical control sample PiN diode characteristics, this equated to an improvement of 8% and 23% for VF and Ron,diff, respectively. From analysis of the reverse recovery characteristics, the carrier lifetime of the PiN diodes oxidized at 1500°C was found to be 1.05 μs, which was an improvement of around 30% compared to the control sample PiN diodes.

Recently, much attention has been devoted to trilayer graphene because it displays stacking and electric field dependent electronic properties well-suited for electronic and photonic applications [1-8]. Several theoretical studies have predicted the electronic dispersion of Bernal (ABA) and rhombohedral (ABC) stacked trilayers. However, a direct experimental visualization of a well-resolved band structure has not yet been reported. In this work, we obtain large area highly homogenous quasi-free trilayer graphene (TLG) on 6H-SiC(0001) and measure its electronic bands via angle resolved photoemission spectroscopy (ARPES). We demonstrate by low energy electron microscopy measurements that that trilayer domains on SiC extend over areas of tens of square micrometers. By fitting tight-binding bands to the experimental data we extract the interatomic hopping parameters for Bernal and rhombohedral stacked trilayers. For ABC stacks and in the presence of an electrostatic asymmetry, we detect the existence of a band-gap of about 120 meV. Notably our results suggest that on SiC substrates the occurrence of ABC-stacked TLG is significantly higher than in natural bulk graphite. Hence, growing TLG on SiC might be the answer to the challenge of controllably synthesizing ABC-stacked trilayer – an ideal material for the fabrication of a new class of gap-tunable devices.

Electrical performance and reliability of SiC Junction Transistors (SJTs) and Schottky rectifiers are presented. The 650 V/50 A-rated SiC SJTs feature current gains (β) up to 110 at room-temperature, 70 at 250°C, and stable breakdown characteristics. Single current pulse measurements indicate an almost invariant β up to 800 A/cm2 at 175°C – a measure of the SOA boundary for pulsed current SJT operation. Lower than 5 mA/cm2 leakage currents are measured on the SJTs at the rated blocking voltage and at 250°C. 1200 V Schottky rectifiers designed for high-temperature operation display < 3 mA/cm2 leakage currents up to 250°C. A 10x reduction in leakage current and 23% reduction in junction capacitance are observed when compared to the nearest competitor. The high-temperature Schottky rectifiers and SJTs display stable breakdown voltages and on-state characteristics after long-term HTRB stressing. A significant improvement in current gain stability is achieved by fine-tuning the fabrication process.

We present the characteristics of a high temperature CMOS integrated circuit process based on 4H silicon carbide designed to operate at temperatures beyond 300°C. N-channel and P-channel transistor characteristics at room and elevated temperatures are presented. Both channel types show the expected low values of field effect mobility well known in SiC MOSFETS. However the performance achieved is easily capable of exploitation in CMOS digital logic circuits and certain analogue circuits, over a wide temperature range.

Data is also presented for the performance of digital logic demonstrator circuits, in particular a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. Devices are packaged in high temperature ceramic dual in line (DIL) packages, which are capable of greater than 300°C operation. A high temperature “micro-oven” system has been designed and built to enable testing and stressing of units assembled in these package types. This system heats a group of devices together to temperatures of up to 300°C while keeping the electrical connections at much lower temperatures. In addition, long term reliability data for some structures such as contact chains to n-type and p-type SiC and simple logic circuits is summarized.

The silicon carbide (SiC) market is gaining momentum hence productivity in device manufacturing has to be improved. The current transition from 100 mm SiC-wafers to 150 mm SiC-wafers requires novel processes in the front-end as well as the back-end of SiC-chip production. Dicing of fully processed SiC-wafers is becoming a bottleneck process since current state-of-the-art mechanical blade dicing faces heavy tool wear and achieves low throughput due to low feed rates in the range of only a few mm/s. This paper presents latest results of the novel dicing technology Thermal Laser Separation (TLS) applied for separating SiC-JFETs. We demonstrate for the first time that TLS is capable of dicing fully processed 4H-SiC wafers, including back side metal layer stacks, process control monitoring (PCM), and metal structures inside the dicing streets with feed rates up to 200 mm/s. TLS thus paves the way to efficient dicing of 150 mm SiC-wafers.

In our previous studies [1-3], four kinds of stacking faults in 4H-SiC bulk crystal have been distinguished based on their contrast behavior differences in synchrotron white beam x-ray topography images. These faults are Shockley faults, Frank faults, Shockley plus c/2 Frank faults, and Shockley plus c/4 Frank faults. Our proposed formation mechanisms for these stacking faults involve the overgrowth of the surface outcrop associated with threading screw dislocations (TSDs) or threading mixed dislocations (TMDs) with Burgers vector of c+a by macrosteps and the consequent deflection of TSDs or TMDs onto the basal plane. Previous synchrotron x-ray topography observations were made in offcut basal wafers using transmission geometry. In this paper, further evidence is reported to confirm the proposed stacking fault formation mechanism. Observations are made in axially cut slices with surface plane {11-20}. Several kinds of stacking faults are recognized and their contrast behavior agrees with the four kinds previously reported. Direct observation is obtained of a Shockley plus c/4 Frank stacking fault nucleating from a TMD deflected onto the basal plane. The contrast from stacking faults on the basal plane in the axial slices is enhanced by recording images after rotating the crystal about the active -1010 reflection vector enabling a broader projection of the basal plane.

Two n+-i-p 6H-SiC diode families with P+ ion implanted emitter have been processed with all identical steps except the post implantation annealing: 1300°C/20min without C-cap has been compared with 1950°C/10min with C-cap. The analysis of the temperature dependence of the reverse current at low voltage (-100V) in the temperature range 27-290°C shows the dominance of a periphery current which is due to generation centers with number and activation energy dependent on the post implantation annealing process. The analysis of the temperature dependence of the forward current shows two ideality factor n region, one with n = 1.9/2 at low voltage and the other one with 1 < n < 2 without passing through 1 for increasing voltages. For both the diode families the current with n = 1.9/2 is a periphery current due to recombination centers with a thermal activation energy near the 6H-SiC mid gap. In the forward current region of 1 < n < 2, the two diode families show different ideality factor values which could be attributed to a different post implantation annealing defect activation.

An alternative approach for reduction of interface traps density at 4H-SiC/SiO2 interface is proposed. Silicon nitride / silicon oxide stack was deposited on p-type 4H-SiC (0001) epilayers and subsequently over-oxidized. The electrical characterization of the interface was done by employing metal-oxide semiconductor (MOS) devices, inversion-channel MOS devices and lateral MOS field effect transistors (MOSFETs).

Although 3C-SiC has a narrower bandgap than 4H-SiC, it is the only SiC polytype that can be grown directly over large area silicon substrates. It has the potential to provide a more economical choice than 4H-SiC for intermediate power devices, such as inverters for electric vehicles. To fabricate a vertical device on 3C-SiC, the Si substrate is usually removed either by etching or polishing. Neither of these processes is economical nor efficient. In this paper we propose a lateral Schottky diode design for 3C-SiC on Si structure. 2D finite element simulations using ATLAS showed that a breakdown voltage beyond 1200 V can be achieved with a 4 μm thick epilayer. Physical models used for 3C-SiC/Si power devices simulations are introduced. Advantages of lateral 3C-SiC/Si diodes over free standing 3C-SiC are also discussed.

In this paper, single crystal 4H-SiC MEMS devices with n-p-n epitaxial structure was fabricated. A dopant-selective photoelectrochemical etching technique was applied to etch the sacrificial p-type SiC layer to release n-type SiC suspended structures on n-type SiC substrate. The selective etching was achieved by applying a bias which employs the different flat-band potentials of n-SiC and p-SiC in KOH solution. Such MEMS devices have the potential to fully exploit the superior properties of single crystal SiC for harsh environment operation, as well as mature epitaxial growth and device fabrication of 4H-SiC. The n-p-n structure, together with the previously reported p-n structure, extends the capability of monolithic integration between MEMS with electronic devices and circuits on SiC platform.

Carbon nanotube (CNT) and graphene films form on silicon carbon (SiC) using a metal-catalyst-free thermal decomposition approach. In this work, the growth conditions used in the decomposition process are varied to investigate their impact on the type and quality of carbon allotrope formed on the SiC substrate. The nanostructure growth is performed using two approaches, both of which involve intense heating (1250-1700oC) under moderate vacuum conditions (10-2 – 10-5 Torr) without the aid of carbon rich feed gases or metal catalysts commonly used in Chemical Vapor Deposition (CVD) growth approaches. The first growth method uses a graphite resistance furnace capable of annealing wafer-sized samples. The second approach uses a high-intensity laser to heat a micro-meter scale spot size. The high-intensity laser heats the illuminated area of the SiC substrate while under vacuum conditions, resulting in a small-scale growth process similar to the conventional resistance furnace technique. Unique to this micro-scale approach is that in situ Raman spectroscopy is performed yielding instantaneous characterization of the resultant carbon nanostructure as it is formed. The laser-induced growth mechanism enables the impact of varied background vacuum pressures and temperatures to be evaluated in situ. This work reports the findings for various parameter sets implemented during growth, and provides insight into the physical mechanism influencing the growth process.

An actual trend to enhance solar cells efficiency is to build multijunction cells, creating a bandshape wavelength collection. However, the best multijuction cells are actually made of III-V compounds when silicon and its alloys don’t lead to high efficiency devices. In this article, we study a 3C-SiC/Si heterojunction as a first step for 3C-SiC/Si tandem cells. Four samples were fabricated by depositing 3C-SiC on Si wafers with different SiC doping levels. Simulations of the structures are performed, as well as optical and electrical characterizations of the heterojunction cells.