The use of Rapid Thermal Processing (RTP) as a processing tool in semiconductor technology is still increasing and and becoming more diverse. The use of RTP in a reactive mode for film growth and deposition is an important new direction. The strong interest in III-V compound annealing studies represents one of the most important application areas. Although RTP is predominantly exploratory and developmental in nature it is slowly being introduced into the manufacture of Si devices. The technological necessity for the greater use of RTP in routine production will depend on either demonstrated productivity/cost advantages or on some intrinsic advantage of RTP. The intrinsic advantages of RTP are due to the single wafer processing nature of the operation or due to the possibility of selectively enhancing one desired process over another undesired reaction in a partically fabricated structure. Although significant impovements in commercially available reactors have been made in the last several years, better temperature measurement and control and particularly temperature uniformity of the wafer are still sorely needed.

Surface layer damage of boron implanted (100) silicon crystals were characterized by x-ray rocking curves using computer fitting procedures. The implantation was carried out at ion energy of 130 KeV with the dose of 1*1016 atoms/cm2. The in-depth strain distribution of the surface layer after rapid thermal annealing was discussed based on x-ray rocking curve observation. It is clearly revealed that the strain profile reverses completely from the positive (tensile) strain in the as-implanted condition to the negative (compressive) strain after annealing. This change is ascribed to the incorporation of boron atoms from interstitial sites to substitutional positions. The results were also compared with transmission electron microscopy (TEM) observations.

High doses: 1, 3 and 6×1015/cm2 of Ga71+ ions were implanted into <100> silicon at 100keV and annealed in the temperature regime of 550-675° C for seconds to tens of seconds. Two different annealing rigs were used; however the physical and electrical results obtained from each provided remarkably similar results.

We have observed a regrowth rate/dose dependency through both our physical and electrical measurements that provide surprisingly good correlation. We also note that for the highest dose complete solid phase epitaxial regrowth is inhibited, and for temperatures as low as 640°C and times as short as 9sec. onset of movement of the gallium toward the surface is observed. We also show that extremely high free carrier concentrations of gallium can be obtained under the correct anneal conditions.

Scanning electron beam annealing techniques have been applied to the study of diffusion of implanted arsenic and boron difluoride. Electron beam anneals over the time range 0-180s (at Tmax), with peak temperatures in the range 1100-1200°C have been performed on uniformly implanted samples. Controlled slow cooling has been performed for some samples. Direct sample temperature measurements were made using a dual-colour pyrometer under control of a microcomputer, which provided data-logging and feedback control of temperature. The accurate temperature control achieved using this system is important for realistic diffusion modelling.

Measurement of the resulting chemical and electrical dopant profiles, using SIMS, RBS and spreading resistance methodshas shown the presence of non-equilibrium diffusion at short times [6]. Channelling RBS studies used to investigate the activation and clustering behaviour of arsenic during the first stages of these very rapid anneals is reported.

Modelling of the arsenic diffusion occuring for a range of implant doses subjected to these anneals has been performed,applying avariety of models, including a dynamic clustering model. This dynamic clustering model, based upon an equilibrium cluster model and a measured de-clustering rate, has been shown previously to give good agreementwith experiment. Forthese experiments, a modified de-clustering coefficient was needed to model the diffusion occuring for a wider range of arsenic implants. A solution of the Poisson equation for the internal electric field has also been incorporated.

DLTS techniques have been used to study the defects remaining in diodes fabricated using these implagts andanneals. Trap densities of <5×1010cm−3 and leakages of <2×10−9 A.cm2 at −5V have been measured for the best devices, similar tothose observed for control furnace anneals.

Experimental results on the diffusion and precipitation of In and B doubly implanted into Si, followed by rapid thermal treatment are reported. It was observed that In redistributes itself and accumulates in defected regions. The amount of motion of each species is enhanced by the presence of the other. While the B influences In diffusion probably through the same mechanism that leads to concentration enhancement, the effect of In on B is not clear. There is no correlation with strain and no apparent chemical effects. Also the presence of B facilitates the sweeping out of In during low temperature solid phase regrowth.

Impurity diffusion induced by rapid thermal annealing (RTA) has been investigated for low energy B and BF2 implants in crystalline and preamorphized Si. A 50 keV 2×1015/cm2 Si self-implant was used for preamorphization. Samples were annealed with an oxide cap in an AG Associates HEATPULSE system (model 210T). Prior to the impurity depth profiling measurements, the SiO2 was removed with dilute HF. Significant B diffusion to theSiO2/Si interface was observed for a 1050°C/10 s anneal of 10 keV 3×1015/cm2 implanted;11B in crystalline and preamorphized Si. B interfacial concentrations were comparableto peak concentrations in unannealed samples. Diffusion of B and F to the SiO2/Si interface, and impurity gettering by ion straggling damage were observed for a 1050°C/10 s anneal of 45 keY 3×1O15/cm2 implanted 49BF2 in crystalline Si.though a loss F was apparent.

Depth profiles were determined with nuclear reaction analysis (NRA) [1-3], specifically the 11B(ρ,α0)8 Be(ER=163 key) [4] and 19F(ραγ)160 (ER - 340 keV) [5] reactions for 1lB and 19F profiling, respectively. This technique is sensitive to impurities at or near the surface and can reveal impurity diffusion to near-surface regions not usually detectable with secondary ion mass spectrometry (SIMS). NRA depth profiling has shownthat RTA can result in significant impurity diffusion to the SiO2/Si interface for B implanted in crystalline and preamorphized Si, and BF2 implanted in crystalline Si. Impurity concentrations at the interface are estimated to be in excess of 1020/cm3 for the implantation and annealing conditions used in this report. BF2 implanted in preamorphized Si showed greatly reduced impurity concentrations at the interface. A knowledge of the impurity concentrations at the substratesurface or the SiO2/Si interface becomes increasingly important as device dimensions decrease. Matrix effects make such measurements difficult with SIMS.

Rapid Thermal Processing is being evaluated in the IC industry as a way to meet the thermal budget requirements of reduced scaling in high performance Si IC's. As scaling is reduced and alternative processing is used, the study of low level interfacial impurities is expected to become more important. An example is presented here for the redistribution of interfacial impurities under RTP for polysilicon capped silicon similar to that proposed for shallow junction bipolar transistors.

We demonstrate a clear advantage for high-temperature, short time annealing to induce intentional, complete epitaxial alignment of arsenic implanted, 0.5 μm-thick polysilicon films on (100) silicon, while minimizing arsenic outdiffusion into the substrate. Using MeV ion channeling and cross-sectional electron microscopy, epitaxial alignment was studied in the 1050-1150 °C temperature range, for arsenic doping concentrations between 1 and 10 × 1020 cm−3. The alignment efficiency increases dramatically with chemical arsenic concentration in this range. An arsenic concentration of 1020 cm−3 yields alignment behavior which proceeds from the polysilicon/single-crystal interface. Between 1 and 5 × 1020 cm×3, the random grain growth can exceed the rate of alignment, and large grain, highly oriented polycrystalline films can result from the RTA. For 0.5 μm-thick polysilicon films with an average doping of 1021 cm×3, the rate of achievement of a high degree of epitaxial alignment exceeds the rate of arsenic penetration into the substrate at temperatures ≥ 1150 °C.

Bipolar transistors with 0.5 μm-thick emitter contacts and polysilicon dopings of 5 and 10 × 1020 cm×3 show less variation in base current when subjected to RTA (T ≥ 1100 °C) compared to devices annealed in a furnace in the 900 to 1000 °C range, while retaining the advantage over metal contacts.

We have found that arsenic implanted into SiO2 segregates at high temperatures in an oxygen-free ambient into spherical, As-rich inclusions of 50 to 500A in diameter. The phase separation prevents diffusion of arsenic, even at temperatures as high as 1400 °C. However, the As-rich inclusions or droplets can be easily moved in a temperature gradient. They migrate towards the heat source at a rate of 2300A /hour in a gradient of 0.14 °C/μm, at 1405 °C, permitting their efficient removal from the oxide and into silicon. We propose a model to explain the dependence of droplet velocity on their size.

The absorption of CO2 laser radiation in doped silicon is dominated by free-carrier transitions, which is an extrinsic absorption property. For applications where one would like to preferentially deposit the pulse energy in heavilydoped layers, the CO2 laser is found to be preferable to other laser systems that oscillate at a photon energyexceeding the bandgap.The advantages of laser processing with below-bandgap radiation are illustrated by three different applications that areeither impossible or much more difficult to achieve with a visible or ultraviolet laser: (1) the melting of buried layerswithout melting the material that encapsulates the molten layer, (2) the melting of shallow layers at the surface, and(3)the annealing of lattice imperfections caused by high-temperature diffusion of phosphorus dopants into small diffusion wells.

The viability of Gas Immersion Laser Doping (GILD) for VLSI processing of ultra shallow junctions is assessed using chemical, electrical and structural characterization of boron doped diodes. Diodes with good ideality factors (1.1) overarange of junction depths (50nm Xj 200 nm) have been fabricated by GILD. This process uses a pulsed XeCI excimer laserincident on a silicon surface saturated with B2H6.

Dopant profiles as a function of laser energy and number of pulses aredetermined using Secondary Ion Mass Spectrometry(SIMS). For low energy or a large number of pulses, comparison with computer modelling suggests the junction is determined by melt depth. For higher laser energy and few pulses, liquid phase diffusion limits the depth of dopant incorporation.

Leakage current measurements as a function of diode perimeter to area (P/A) ratio and Deep Level Transient Spectroscopy (DLTS) suggest that leakage occurs along the diode perimeter, and is dueto point defects generated from thermal stresses during melt regrowth. Diodes show good I-V characteristics after GILD alone, yet subsequent rapid thermal annealingisfound to further reduce leakage currents, probably due to relief of thermal stresses. Sheet carrier densities from Halleffect measurements show that 5 - 10% of the boron is activated, with doping levels exceeding 1020 cm−3 in some samples. Transmission Electron Microscopy (TEM) demonstrates that reasonable crystalline quality is maintained for moderate GILD conditions with a defect density at the surface of approximately 108 cm−2 .For higher laser energy with boron incorporation exceeding solid solubility, TEM shows stacking faults along <110>directions. Electron diffraction on highly doped samples shows extra spots indicating a high degree of strain in the doped layer.

Rapid thermal processing of silicon in oxygen and ammonia ambients is an attractive technique for the growth of thin dielectrics such as silicon nitride, silicon dioxide, nitrided oxides, oxidized nitrides, and application-specific (composition-tailored) insulators. Multicycle rapid thermal growth processes are suitable for dielectric engineering and in-situformation of thin layered insulators with a variety of controllable oxygen and nitrogen compositional depth profiles by appropriate design of the temperature and ambient gas cycles. The growth and electrical properties of various dielectrics rapidly grown by the state-of-the-art techniques and their corresponding device performance are examined. Rapid thermal processing and microwave plasma generation have been combined in a novel custom-made multipurpose reactor for rapid plasma-enhanced multiprocessing of Si, Ge, and GaAs. Thin germanium nitride dielectrics can be formed by rapid thermal or plasma nitridation for germanium CMOS applications. Combination of in-situ rapid plasma nitridation followed by silicon nitride deposition may prove to be effective for MIS structures and surface passivation on GaAs. These new applications of rapid thermal/plasma processing are additional steps towards realization of fully RTP-based Si VLSI fabrication processes and development of new devices and technologies on other semiconductor materials.

This paper discusses the local atomic structure in silicon dioxide films formed by the oxidation of silicon in dry oxygen in a temperature range between 850 and 1150°C. The films grown at 850°C were subjected to rapid thermal annealing (RTA)at temperatures between 800 and 1200°C and for periods of time ranging from 1 to 100 seconds. The local atomic structure has been studied via infrared (IR) spectroscopy and ellipsometry. We discuss the temperature dependence (with respect to both oxidation temperature, and annealing temperature [and time]) of the frequency, v, and linewidth, δv, of the Si-O-Si bond stretching vibration, and the index of refraction, n, at 632.8 nm. We make comparisons with silicon dioxidefilms deposited by remote plasma enhanced chemical vapor deposition (RPECVD) at temperatures between 100 and 400C and subjected to high temperature annealing (850 to 1050°C). We find that the variations in v, δv and n with growth, deposition and annealing can be understood in terms of systematic variations in the magnitude of the bond angle, 2e, at the oxygen atom bonding sites.

Thin oxides with thicknesses in the range of 150 to 300Å were grown on lOO-mm <100> Si wafers in a commercial RTP reactor. Growth temperatures and times were llO0-1200°C for 60-180 seconds in 100% 02 at 1 atmosphere. Oxide thickness uniformity was measured using ellipsometry; contour maps of thickness uniformity will be presented. The standard deviation wascalculated to be 2-2.5% within 5 mm of the edge using a method which weights the area represented by each of 45 data points per wafer. In order to correct for dynamic changes in temperature uniformity, a new annealing method was developed.Results on wafer-to-wafer uniformity will be presented. Improvements achieved by post-oxidation annealing in N2 and electrical uniformity of films will be discussed.

This paper presents kinetic data for the rapid thermal oxidation (RTO) of <100 silicon using a wall stabilized low pressure arc lamp as the heating source. The data shows a single activation energy of 1.31 eV over the temperature range of 900°C to 1200°C and times of 60 seconds to 240 seconds. Comparisons are made with published kinetic data of RTO using tungsten-halogen lamp source [1] and with furnace oxidation kinetics for short times (<240 sec.) [2]. “Wet” oxidation results using O2:H2 as the oxidizing ambient reveal a lower activation energy and preexponential coefficient than the dry oxidation. Also presented are results using an experimental set-up which exhibits ultraviolet enhanced oxidation.

Thin layers of SiO2 (60-300 Å) were fabricated by rapid thermal oxidation (RTO). Growth rate on (100) and (111) Si was determined. Two different high-temperature anneal cycles were used to reduce the interface state density. Work function difference between metal and semiconductor depends upon technology and can be attributed to the changes in Si-SiO2 barrier height.

The original intent of this study was to compare rapid thermal, thin (80-100Å) gate oxides with standard, furnace-grown, thin gate oxides for endurance. Wafer processing before gate oxide growth was chosen to duplicate processing used ina typical non-volatile memory product. In particular, care was taken to duplipate pre- and post- gate growth processing of field oxide isolated polysilicon capacitors for all wafers in order to eliminate the previous difficulties in comparing oxides when different cleans and processing steps are used.[1] Substrate defects, atypical to this process, were presumably introduced during the initial wafer cleaning and scattered the time-to-breakdown (TTB) values during a constant current stress of these oxides to the point where statistical comparison of TTB averages was dubious. However, for unannealed wafers and for post polysilicon definition heat treatments of 900°C, RTO oxides grown with HCL had the same oxide trapping rate as the furnace oxides grown with TCA and RTO oxides grown in pure O2 had a faster trapping rate. Higher temperature post polysilicon definition heat treatments had different effects. RTO oxides exhibited better yield than the furnace oxides. These results illustrate the differences between RTO and furnace oxidation in the presence of non-ideal wafer substrates.

In this paper the kinetics of initial nitridation of thermal oxides is studied by using rapid thermal nitridation of thin oxides. FTIR and AES were used to investigate the chemical properties of nitrided oxide films. The amount of the nitrogenincorporated in and the oxygen escaped from 100Å oxides has been characterized quantitatively as a function of RTN conditions. Results show that RTN at 1100° for 120s incorporates about 85% and 12% of the maximum nitrogen concentration value at oxide surface and bulk, respectively. The nitrogen pile up peak at interface can be seen after RTN at 1100°C with the time as short as 5 s. Study of the effects of the nitridation temperature and the original oxide film thickness indicates that the reaction species has permeated through oxides before effective replacement reaction takes place. The diffusion coefficient of the permeating species is estimated of the value larger than 40−13cm2/s.

Rapid thermal processing has been used to grow high quality, low defect density, low mobile charge, dielectric films of oxide and nitrided oxide. Suitable annealing can lower the fixed charge and interfacial trap density present in these filmsto acceptably low levels. Both RTA and RTN were shown to improve the dielectric properties of the grown oxides. These filmsshould be strong candidates for use in high density, shallow junction, integrated circuits where a minimal time/temperature constraint is imposed on further processing after diffusion.

Rapid thermal oxidation of silicon has been performed in a tungsten-halogen system (AG-410) and a water-wall arc lamp system (Eaton ROA-400). Growth kinetics of the oxides are studied with particular attention to ramp-up ambient conditions, dwell time, maximum wafer temperature and difference in activation energies. These parameters are characterized using ellipsometry in order to measure system bias with respect to growth rate and breakdown. Experiments were designed to identify the differences in the initial enhanced growth conditions, and their effect on growth kinetics during the dwell cycle.