We performed first-principle simulation for the study of oxygen vacancy defect in rutile TiO2 based on density functional theory. The effects of a vacancy on the electronic structure of rutile TiO2 were studied. Here we have employed neutral and charged oxygen vacancy in the supercell to address the resistance switching mechanism. Neutral vacancy induces the band gap states at deep level, ∼0.7 eV below the conduction band minimum, which is occupied by highly localized electrons. The calculation results of positively charged oxygen vacancy show that larger atomic relaxation surrounding oxygen vacancy results in the stretching of Ti-O bond around vacancy, thus band gap states are formed near the conduction band minimum.

In this paper, we develop a new method based on ultra-low-energy ion implantation through a stencil mask to locally fabricate Si nanocrystals in an ultrathin silica layer. We perform a 1 keV Si implantation with doses of 5×1015 Si+/cm2, 7.5×1015 Si+/cm2 and 1×1016 Si+/cm2 in a 7 nm thick silicon oxide layer through stencil mask apertures ranging from 1μm up to 5 μm. After the mask removal the samples are furnace annealed at a temperature of 1050°C for 90 min under N2 atmosphere. The samples are then characterized by mapping the implanted and non-implanted areas by atomic force microscopy and photoluminescence spectroscopy. The intensity and the wavelength of the PL peak are found to depend on the implanted NCs cell size. A slight blue shift from 730 nm up to 720 nm is observed with decreasing cell size. Simultaneously, the PL intensity decreases and the signal vanishes for submicron features (which should contain 102 to 103 NCs). AFM microcopy performed on the implanted regions shows that the well-known oxide swelling usually observed after NCs synthesis decreases from 3.5 nm down to 0 as the cell size decreases. This result demonstrates that the effective implanted dose clearly decreases with the size of the cells. This effect is probably due to an electrostatic charging of the Si3N4 membrane despite the metallization treatments applied to the mask surface.

Ferroelectric random access memory (FeRAM) is believed to be the most promising candidate for the next generation non-volatile memory due to its fast access time and low power consumption. Fabrication technologies of FeRAM can be divided into two parts: CMOS technologies for circuits which are standard and can be shared with traditional IC process line, and process relating to ferroelectric which is separated with CMOS process and defined as backend module. This paper described technologies for integrating ferroelectric capacitors into standard CMOS, mainly about modeling of ferroelectric capacitors and backend fabrication technologies. Hysteresis loop of the ferroelectric capacitor is the basis for FeRAM to store data. Models to describe this characteristic are the key for the design of FeRAM. A transient behavioral ferroelectric capacitor model based on C-V relation for circuit simulation is developed. The arc tangent function is used to describe the hysteresis loop. “Negative capacitance” phenomenon at reversing points of applied voltage is analyzed and introduced to the model to describe transient behaviors of the capacitor. Compact equivalent circuits are introduced to integrate this model into HSPICE for circuit simulation. Ferroelectric materials fabrication, electrodes integration and etching are the main technologies of FeRAM fabrication process. An metal organic chemical vapor deposition (MOCVD) process is developed to fabricate high quality Pb(Zr1-xTix)O3 (PZT) films. Pt is known to cause the fatigue problems when used as electrodes with PZT. Ir is used as electrodes to improve the fatigue property of PZT based capacitors, and mechanism of the fatigue is analyzed. Hard mask is used to reduce the size of the capacitors and damage caused in etching process. In our process, Al2O3 is developed as hard mask, which simplifies the FeRAM backend integration process.

HfO2-based layers prepared by RF magnetron sputtering were studied by X-ray diffraction, infrared absorption spectroscopy and transmission electron microscopy techniques. The effect of the deposition parameters and post-deposition annealing treatment on the properties of the layers was investigated. The amorphous-crystalline transformation of pure HfO2 layers is observed to be stimulated by annealing treatment at 800 ° C. It was found that the incorporation of silicon in HfO2 matrix allows to prevent crystallization of the layers and to shift the crystallization temperature to values up to 900 °C.

The electric-field-induced resistance switching (EIRS) phenomenon on a VO2 planar-type junction fabricated on a Al2O3 (0001) substrate was studied by performing current-voltage (I-V) measurement and optical microscope observation simultaneously. It was confirmed that current density J of the low-resistance-state (LRS) region is maintained constant at approximately 1.6 × 106 A/cm2, while the volume of the LRS region was changed according to the current. A survey of the previous I-V traces on EIRS of VO2 revealed that almost all the junctions so far had shown non-zero V-intercepts, which are attributed to the volume change of the LRS regions. The maintenance of high-J in the LRS region is considered to be related to the electrically-induced metallic phase mechanism reported in perovskite-type manganites.

A nonvolatile memory device with the multi-layered SiC nanocrystals embedded in the SiO2 dielectrics for long-term data storage was fabricated and its electrical properties were evaluated. The SiC nanocrystals were formed by using post thermal annealing process. The transmission electron microscope analysis showed the multi-layered SiC nanocrystals between the tunnel and the control oxide layers. The average size and density of the SiC nanocrystals were approximately 5 nm and 2×1012 cm-2, respectively. The memory window of nonvolatile memory devices with the multi-layered of SiC nanocrystals was about 2.7 V during the operations at ±10 V for 700 ms, and then it was maintained around at 1.1 V after 105 sec.

Recent interest in phase change materials (PCMs) for non-volatile memory applications has been fueled by the promise of scalability beyond the limit of conventional DRAM and NAND flash memory [1]. However, for such solid state device applications, Ge2Sb2Te5 (GST), GeSb, and other chalcogenide PCMs require doping. Doping favorably modifies crystallization speed, crystallization temperature, and thermal stability but the chemical role of the dopant is not yet fully understood. In this work, X-ray Absorption Fine Spectroscopy (XAFS) is used to examine the chemical and structural role of nitrogen doping (N-) in as-deposited and crystalline GST thin films. The study focuses on the chemical and local bonding environment around each of the elements in the sample, in pre and post-anneal states, and at various doping concentrations. We conclude that the nitrogen dopant forms stable Ge-N bonds as deposited, which is distinct from GST bonds, and remain at the grain boundary of the crystallites such that the annealed film is comprised of crystallites with a dopant rich grain boundary.

Memory properties of nickel silicide nanocrystal monolayers embedded in silicon dioxide have been investigated. The nanocrystal layers were produced by thermal annealing of a sandwich structure comprised of ultrathin Ni film (0.2 nm) sandwiched between two silicon-rich oxide (SiO1.57) layers. Average diameter and areal density is about 2.9 nm and 1.3×1012 cm-2, respectively. Capacitance-voltage (C-V) measurements are shown to have C-V characteristics suitable for nonvolatile memory applications, including large memory window (∼ 10 V), long retention time ( > 107 s), and excellent endurance ( > 106 program/erase cycles).

The influence of mechanical constraint imposed by device geometry upon the switching response of a ferroelectric thin film memory capacitor is investigated. The memory capacitor was represented by two-dimensional ferroelectric islands of different aspect ratio, mechanically constrained by surrounding materials. Its ferroelectric non-linear behaviour was modeled by a crystal plasticity constitutive law and calculated using the finite element method. The switching response of the device, in terms of remnant charge storage, was determined as a function of geometry and constraint. The switching response under applied in-plane tensile stress and hydrostatic pressure was also studied experimentally. Our results showed that (1) the capacitor's aspect ratio could significantly affect the clamping behaviour and thus the remnant polarization, (2) it was possible to maximise the switching charge through the optimisation of the device geometry, and (3) it is possible to find a critical switching stress at zero electric field and a critical coercive field at zero residual stress.

The crystallization behavior of Ge-Sb phase change materials with variable Ge:Sb ratio X between 0.079 and 4.3 was studied using time-resolved x-ray diffraction, differential scanning calorimetry, x-ray reflectivity, optical reflectivity and resistivity vs. temperature measurements. It was found that the crystallization temperature increases with Ge content from about 130 °C for X = 0.079 to about 450 °C for X = 4.3. For low X, Sb x-ray diffraction peaks occurred during a heating ramp at lower temperature than Ge diffraction peaks. For X = 1.44 and higher, Sb and Ge peaks occurred at the same temperature. Mass density change upon crystallization and optical and electrical contrast between the phases show a maximum for the eutectic alloy with X = 0.17. The large change in materials properties with composition allows tailoring of the crystallization properties for specific application requirements.

The fabrication of NCs is carried out using an innovative method, ultra-low energy (≤5 keV) ion implantation (ULE-II) into thin (6-9 nm) HfO2–based layers in order to form after subsequent annealing a controlled 2D array of Si NCs. The implantation of Si into HfO2 leads to the formation of SiO2–rich regions at the projected range due to the oxidation of the implanted Si atoms. This anomalous oxidation that takes place at room temperature is mainly due to humidity penetration in damaged layers. Different solutions are investigated here in order to avoid this oxidation process and stabilize the Si-phase. Finally, unexpected structures as HfO2 NCs embedded with SiO2 matrix are obtained and show interesting memory characteristics. Interestingly, a large memory window of 1.18 V has been achieved at relatively low sweeping voltage of ± 6 V for these samples, indicating their utility for low operating voltage memory device.

In this paper, the undoped SrTiO3 (STO) and Indium doped STO (SrTi1-xInxO3: STIO) thin films were grown on Pt/Ti/SiO2/Si substrates by pulsed laser deposition with low substrate temperature. For undoped STO film, the influences of the forming processes on their resistive switching properties were studied by current and voltage controlled I-V sweeps, respectively. An obvious current controlled negative differential conductance phenomenon was found in both polarities of the electrical field. However, for low Indium doped STIO (x=0.1), the filament related resistance switching was observed in both the current and voltage I-V sweeps. And for high Indium doped STIO (x=0.2), a resistance switching with a reverse direction change to that in undoped STO can be obtained by a proper forming process. Based on these results, the reversible change of the Schottky like barrier at the grain boundary by the migration of oxygen vacancies were proposed to interpret the mechanism of the resistance switching.

We have fabricated the nano-floating gate memory with the TiSi2 and WSi2 nanocrystals embedded in the dielectrics. The TiSi2 and WSi2 nanocrystals were created by using sputtering and rapidly thermal annealing system, and then their morphologies were investigated by transmission electron microscopy. These nanocrystals have a spherical shape with an average diameter of 2-5 nm. The electrical properties of the nano-floating gate memory with TiSi2 and WSi2 nanocrystals were characterized by capacitance-voltage (C-V) hysteresis curve, memory speed and retention. The flat-band voltage shifts of the TiSi2 and WSi2 nanocrystals capacitors obtained appeared up to 4.23 V and 4.37 V, respectively. Their flat-band voltage shifts were maintained up to 1.6 V and 1 V after 1 hr.

Self-aligned TiSi2 coated Si nanocrystal nonvolatile memory is fabricated. This kind of MOSFET memory device is not only thermally stable, but also shows better performance in charge storage capacity, writing, erasing speed and retention characteristics. This indicates that CMOS compatible silicidation process to fabricate TiSi2 coated Si nanocrystal memory is promising in memory device applications.

Anodic Aluminum Oxide (AAO) was grown both as free-standing membranes and as integrated layers on Si as templates for arrays of magnetoresistive nanowires. These structures will be useful for applications such as current-perpendicular-to-plane giant magnetoresistance (CPP-GMR) sensors, magnetic random access memory (MRAM) and microwave oscillator arrays. As the AAO was formed, using a two-step anodization process, columnar nanopores self-assembled inside the oxide to form a close-packed array. The pore diameters could be varied from 10-60nm by changing the anodization conditions. As the diameter of the AAO nanopores decreased, the distance between the nanopores also decreased. The free-standing membranes had pores with lengths of 17um. The pores that were grown directly onto Si with an adhesion layer of Ti were 600nm in length. In addition to growing these latter pores directly onto Si, they were also grown onto Co/Cu/Co thin films that were evaporated onto the Si. Au nanocontacts were electroplated into these nanopores to study point-contact magnetoresistance and microwave response. For the magnetoresistive nanostructures, multilayered Co/Cu nanowires were fabricated via electrochemical deposition. The samples were measured with vibrating sample magnetometry (VSM) and also using ac and dc magnetotransport systems. The highest magnetoresistance was found in nanowires that had hysteresis loops that were identical as measured in plane and perpendicular to the plane. The highest measured MR (Delta R/R = 11%) of the multilayers was calculated as 33% by subtracting the resistance of the Cu leads on either side of the multilayers from the denominator. Shorter wires are currently under construction to avoid this effect. Spin transfer torque (STT) was also measured in the samples. For 10-60nm diameter nanowires, the change in resistance due to STT was around 6% which represents the full magnetoresistance of the larger wires, but only half that of the smaller nanowires. It is therefore concluded that the 10-nm Co layers do not align antiparallel to parallel as fully at the switching current density of JAP-P = 2.7 × 108 A/cm2 compared to the larger wires which switch at JAP-P = 3.2 × 107 A/cm2. With diameters in the 10-60 nm range and integration with Si, these nanostructures have great potential for future nanosensors, MRAM and microwave oscillator arrays.

GeTe-Sb2Te3 pseudobinary compounds are attracting considerable attention as phase change materials for optical disk and phase change random access memory (PRAM). In these compounds, Ge2Sb2Te5 (GST) has been used for an optical disk memory such as DVD-RAM because the crystallization by laser beam heating is very fast (∼20ns). Recently, the GST has been much considered as material for PRAM and, therefore, the electrical resistance change due to crystallization and the phase change by applying an electrical current have been widely investigated. On the other hand, although GeTe compound has been suggested as the phase change material for the optical disk by Chen et al in 1986, the study focusing on the phase change material for PRAM is limited. Since GeTe is known to show the phenomenon of electrical switching, this compound has a potential of PRAM. In this study, the electrical resistance and crystalline structural changes on crystallization process in Ge-Te thin films were investigated.

Films of amorphous Ge100–xTex (x : 46-94) with 200 nm thickness were deposited by sputtering of GeTe alloy target or co-sputtering of GeTe and Te targets on SiO2/Si substrates. In-situ electrical resistance measurements during heating process of these films were performed by two point probe method in a heating rate of 2∼50°C/min. X-ray diffraction (XRD) analysis was employed for the structural identification of thin films for 10-60° in 2′ using X-ray diffractometer with Cu-K. Transmission electron microscope (TEM) analysis was carried out to investigate the microstructure and to identify crystalline structure. The compositions of these films were confirmed by energy dispersive X-ray spectroscopy (EDS) attached TEM.

All as-deposited Ge-Te films were confirmed amorphous by XRD and TEM. From the in-situ electrical resistance measurements, it is found that resistance change with crystallization process depends on the composition and the stoichiometric GeTe compound shows abrupt electrical resistance change at around 190 °C. The crystallization temperature of GeTe was higher than that of GST and resistance difference between the amorphous and the crystal was also larger. While the electrical resistance of GST film gradually decreased with increasing temperature after the crystallization at around 160 °C, that of GeTe film showed small temperature dependence after crystallization. It was found by X-ray measurement observation that the amorphous GeTe compound film crystallized first into a cubic state, and then into a stable rhombohedral state by further heating. The crystallization kinetics of Ge-Te thin films will be also presented.

Electric-induced resistance switching (EIRS) effect based on transition metal (TM) oxides, such as perovskite manganites (Pr1-xCaxMnO3, La1-xCaxMnO3) and binary oxides (NiO, TiO2 and CoO) etc, has attracted great interest for potential applications in next generation nonvolatile memory known as resistance random access memory (RRAM). Compared with other nonvolatile memories, RRAM has several advantages, such as fast erasing times, high storage densities, and low operating consumption. Up to date, the switching mechanism, property improvement and new materials exploitation are still the hotspots in RRAM research.

In this report, the main results of resistance switching of two kinds of TM oxides including La0.7Ca0.3MnO3 and TiO2 were presented. Based on the I-V characteristics, the field-direction dependence of resistance switching (RS) behavior, and the conduction process analysis, the EIRS mechanisms were studied in detail. For the La0.7Ca0.3MnO3 film, the EIRS mechanism was related to the carrier injected space charge limited current (SCLC) conduction controlled by the traps existing at the interface between top electrode and La0.7Ca0.3MnO3 film. The RS behavior is produced by the trapping/detrapping process of carriers under different voltages. For the TiO2 film, both unipolar and bipolar RS behavior can be obtained in our experiments. The interface controlled filamentary mechanism was proposed to explain the unipolar EIRS in nanocrystalline TiO2 thin films, while the bipolar RS behavior may be related to the charge trapping or detrapping effect. In addition, it was confirmed that the I-V sweeps in vacuum environment, the applying of asymmetry pulse pairs and the oxygen annealing of films can improve the endurance of the EIRS devices. Our researches will provide some meaningful clues to understanding the EIRS mechanism and some useful pathways for the development of RRAM devices.

The crystallization of amorphous Ge2Sb2Te5 thin films has been studied by X-ray diffraction (XRD) and transmission electron microscopy (TEM). The analysis has been performed on partially crystallized films, with a surface crystalline fraction (fS) ranging from 20% to 100%. XRD analysis indicates the presence, in the partially transformed layer, of grains with average lattice parameters higher than that of the equilibrium metastable cubic phase (from 6.06 Å at fS=20% to 6.01 Å at fS=100%). The amorphous to crystal transition, as shown by TEM analysis, occurs through the nucleation of face-centered-cubic crystal domains at the film surface. Local dimples appear in the crystallized areas, due to the higher atomic density of the crystal phase compared to the amorphous one. At the initial stage of the transformation, a fast bi-dimensional growth of such crystalline nucleus occurs by the generation of transrotational grains in which the lattice bending gives rise to an average lattice parameter significantly larger than that of the face-centered-cubic phase in good agreement with the XRD data. As the crystallized fraction increases above 80%, dimples and transrotational structures start to disappear and the lattice parameter approaches the bulk value.

A summary is presented of our theoretical and experimental work over more than two years related to switching in chalcogenide glass phase change memory. As a significant addition to the well known experiments, we have studied switching under considerably lower voltages and elevated temperatures, as well as the statistics of switching events and relaxation oscillations. Our analytical theory, based on field induced crystal nucleation, predicts all of our observed features and their dependencies on material parameters.

The nanocrystalline ZnO embedded Zr-doped HfO2 high-k dielectric has been made into MOS capacitors for nonvolatile memory studies. The device shows a large charge storage density, a large memory window, and a long charge retention time. In this paper, authors investigated the temperature effect on the reliability of this kind of device in the range of 25°C to 175°C. In addition to the trap-assisted conduction, the memory window and the breakdown strength decreased with the increase of the temperature. The high-k film's conductivity increased and the nc-ZnO's charge retention capability decreased with the increase of temperature. The nc-ZnO retained the trapped charges even after the high-k film broke down and eventually lost the charges at a higher voltage. The difference between these two voltages decreased with the increase of the temperature.