The relationship between silicide thickness, sheet resistance and silicon consumption is experimentally checked for Co-disilicide and Ni-monosilicide. The reverse bias leakage current of shallow Ni-silicided and Co-silicided square diodes is compared for varying junction depth and varying silicide thickness. A lower reverse bias leakage current is obtained for a Ni-silicided shallow junction as compared to its Co-silicided counterpart. This can be attributed to the reduced silicon consumption. The Ti cap does not play an active role during the Ni-silicidation of narrow active area and poly lines. It is shown that a Ni-silicidation process is scalable without Ti cap.

Amorphous thin films of composition TixSi1−xO2 have been grown by low pressure chemical vapor deposition on silicon (100) substrates using Si(OEt)4 and either Ti(OiPr)4 or anhydrous Ti(NO3)4 as the sources of SiO2 and TiO2, respectively. The substrate temperature was varied between 300 and 535°C, and the precursor flow rates ranged from 5 to 100 sccm. Under these conditions growth rates ranging from 0.6 to 90.0 nm/min were observed. Films were amorphous to X-rays as deposited and SEM micrographs showed smooth, featureless film surfaces. Cross-sectional TEM showed no compositional inhomogeneity. RBS revealed that x (from the formula TixSi1−xO2) was dependent upon the choice of TiO2 precursor. For films grown using TTIP-TEOS x could be varied by systematic variation of the flow of N2 through the precursor vessels or the deposition temperature. For the case of TN-TEOS x remained close to 0.5. The results suggested the existence of a specific chemical reaction between TN and TEOS prior to film deposition.

The CVD of zirconium dioxide (ZrO2) films from zirconium tetra-tert-butoxide {Zr[OC(CH3)3]4} is also described. The films, which were deposited on Si(100), were characterized by scanning electron microscopy (SEM), transmission electron microscopy (TEM), ellipsometry, X-ray diffraction (XRD), and Rutherford backscattering spectroscopy (RBS). Deposition was studied between ∼380 and 825 °C, and at precursor pressures between 4 × 10−5 and 1 × 10−4 Torr. The kinetics for steady-state growth were studied as functions of temperature and precursor pressure. Results were fit to a two-step kinetic model involving reversible precursor adsorption followed by irreversible decomposition to ZrO2.

Previously we have found that the addition of a thin layer of Co between Ni and the Si substrate dramatically improves the thermal stability of the resulting silicide. Here we describe the use of four different x-ray techniques to obtain complementary information on film structure, providing a possible explanation for the observed thermal stability.

In this paper we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve a low threshold voltage for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not compromise the integrity and electrical reliability of the gate dielectric. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.

A simple and novel salicidation process applying pulsed laser annealing as the first annealing step was used to induce TiSi2 formation. Both Raman spectroscopy and transmission electron microscope results confirm the formation of a new phase of Ti disilicide, the pure C40 TiSi2 after laser irradiation. Direct C54 phase growth on the basis of C40 template bypassing the C49 phase is accomplished at the second annealing temperature as low as 600°C. Line width independent formation of the C54 phase was observed on patterned wafers using this salicidation process and “fine line effect” is thus eliminated.

Bulk Density Functional Theory calculations were performed on Hf and Zr substitutions for Al in κ-alumina. The lowest energy configuration found was an octahedrally coordinated Zr site. Zr dissolution was favorable with an enthalpy of -2eV/unit cell for forming Al1.875Zr0.125O3 from pure Zr and κ-alumina. Hf and Zr substitution for Al atoms introduced empty d-states below the conduction band edge reducing the Eg of pure κ-alumina (7.5eV) to 6.4-5.9eV. The edge of the valence band however remained fixed by the O p-state character. The substitution of Hf and Zr into the alumina structure may lead to a higher dielectric constant, but will also reduce Eg and result in a trade off in tunneling currents in devices.

A reactive Ti capping layer is needed to getter oxygen contamination and to make the cobalt silicidation reaction a more robust process. However, the presence of a Ti capping layer induces two other effects (in addition to the beneficial gettering of oxygen impurities): the formation temperature of CoSi2 is increased and the CoSi2 layer has a strong (220) preferential orientation. Because of the current technological importance of the Ti/Co/Si system, we have made a detailed investigation of the influence of several process parameters (annealing temperature, selective etching, layer thickness) on the nucleation of CoSi2 in the Ti/Co/Si system. Moreover, it is shown that the addition of Ni (i.e. a Ti/Co/Ni/Si or Ti/Ni/Co/Si structure) causes a decrease of the CoSi2 nucleation temperature.

Dichlorosilane based CVD WSix is deposited by the reaction of tungsten fluoride (WF6) and dichlorosilane (SiH2Cl2; DCS). The reaction is thermodynamically favorable and results in WSix film with less fluorine (F) concentration than monosilane (SiH4; MS) based WSix. DCS based WSix shows less expansion of gate oxide and better step coverage than monosilane based WSix. Due to its DCS based stable film stoichiometry, WSix has low resistivity and therefore has been widely applied in ULSI memory devices. However, DCS is a source of chlorine, which is a major impurity. This means special considerations have to be made when using DCS based WSix in comparison with MS based WSix. This work provides evaluation and control of chlorine behaviors in DCS based WSix film.

Current trends in integrated circuit processing project gate insulators with oxide equivalent thicknesses of 1.5 to 1.0 nm. Gate oxides in this thickness range have oxide capacitances of 1 to 5 μF/cm2. When oxide capacitances are this large, traditional high-frequency capacitance-voltage techniques for measuring interface states can be inaccurate. We show that a combination of high and low frequency capacitance-voltage data, along with frequency dependent conductance methods, produce more accurate results.

ZrO2 ([.kappa]∼ 18) was deposited on Si(100) wafers by rapid thermal chemical vapor deposition (RT-CVD) process to replace SiO2 as the gate dielectric material in metal-oxide- semiconductor devices for its high dielectric constant, good thermal stability on silicon, and large bandgap. The deposited films are nearly stoichiometric, amorphous, uniform, and highly smooth, as determined by X-ray photoemission spectroscopy, X-ray diffraction, ellipsometry, and atomic force microscopy. The high resolution transmission electron microscopy (TEM) image shows an interfacial ZrSiO4 layer between ZrO2 and the silicon substrate, and this interfacial layer is verified by thermodynamic calculations and etching resistance measured at the interface. Excellent step coverage was observed for depositing ZrO2 on nanometer scale features with an aspect ratio of 4. The dielectric constant of RTCVD ZrO2 was 15-18, with small C-V hysteresis and low leakage current.

Tungsten silicide (WSix) films, deposited by chemical vapour deposition are normally amorphous in nature, and need to be annealed at high temperature to obtain low resistivity required for interconnections and metallization layers in VLSI circuits. In this paper, we focus on this annealing process for films deposited on Si and SiO2 substrate, and having Si/W ratio of 2.4. The characterization methods used were time-resolved X-ray diffraction, Resistivity measurement, and Rutherford backscattering spectroscopy analysis. We observe that 30 minutes is not sufficient for complete transformation of the WSi2.4 films on Si substrate. We also report on the dependence of annealing behaviour of nonstoichiometric WSixfilm on the substrate type.

This paper reports structural and electrical properties of catalytic-nitrided silicon dioxide (SiO2) films. The surface of SiO2/Si(100) was nitrided at temperatures below 573 K. It was found that the incorporated N atoms are bound to Si atoms and O atoms and located on the top-surface of SiO2. Catalytic-nitrided SiO2 films have small amounts of Si-OH bonds and adequate resistance to boron (B) penetration.

Whisker-originated short in the self-aligned contact (SAC) W polymetal gate was directly observed for the first time. Short points between gate electrodes and poly-Si plugs in the test structure were identified by emission microscope and cross-sectional TEM samples of those points were made by using focused ion beam (FIB).

Whiskers are formed during high-temperature processing such as LP-CVD SiN. We have proposed that NH3 de-oxidation step inserted in the SiN deposition sequence is effective for suppressing whisker growth. [1] In this study it was also confirmed that 600°C NH 3 pre-flow improved leakage current between gate electrode and contact plugs.

In this work, we studied the electrical and thermal stability of Ru and RuO2 electrode on Y-silicate dielectrics in contrast to ZrO2 and Al2O3 dielectrics. Very low resistivity Ru and rutile stoichiometric RuO2 films, deposited via reactive sputtering, were evaluated as gate electrodes on ultrathin Y-silicate, ZrO2 and Al2O3 films for Si-MOS devices. Thermal and chemical stability of the electrodes was studied at annealing temperatures up to 800°C in N2 and subsequently forming gas anneal. XRD and XPS were measured to study grain structure and interface reactions. The morphology of the films was tested by atomic force microscopy (AFM). Electrical properties were evaluated via MOS capacitors. The role of oxygen inside dielectrics was studied by comparing equivalent oxide thickness change as a function of annealing temperature for capacitors with Y-silicate, ZrO2and Al2O3 dielectrics. Good stability of Ru and RuO2 gate electrodes on all dielectrics studied was found. Flatband voltage and gate current as a function of annealing temperature was also studied. It was found that capacitors with Y-silicate after high-temperature anneal had less positive flatband voltage shift than ZrO2 and Al2O3. For capacitors with Ru gate electrode, the significant flatband voltage shift after high temperature anneal could be partially removed by a forming gas anneal.

Recently, selectively deposited SiGeB alloys have been proposed to form ultra-shallow source/drain junctions for 35-70 nm CMOS. The technology provides super-abrupt junctions with above equilibrium dopant activation at temperatures lower than 800°C. In addition to their low resistivities, the lower bandgap of SiGeB provides the potential advantage of reducing the Schottky barrier height and therefore, the junction contact resistance. This is a critical concern for future CMOS technology nodes since the contact resistance will dominate the MOSFET series resistance unless new technologies yielding contact resistivities near 10−8 ω−cm2 are developed. This paper examines the solid phase reactions of Ni and Pt with SiGeB alloys in order to form self-aligned low resistivity contacts. The results show that both Ni and Pt can form germanosilicides with low sheet resistances. Furthermore, both metals can form self-aligned contacts with a contact resistivity near 10−8 ω−cm2.

In this work, AFM and sheet resistance measurements are used to characterize the thermal stability of thin CoSi2 films. We were particularly interested in the influence of different multilayer structures on the topography and surface roughness. Four different multilayer structures (Co/Si, TiN/Co/Si, Ti/Co/Si and Co/Ti/Si) were investigated. Thermal degradation of CoSi2 formed from a standard Co/Si structure is found to have an activation energy of about 4.2 eV, independent of layer thickness (in agreement with previous results by Alberti et al.). A TiN capping layer is shown to improve the thermal stability. However, if the TiN layer is too thick (e.g. 50 nm), a new failure mode is observed: although the TiN prevents grain boundary grooving of the silicide, the thermal stress induced by the TiN causes the CoSi2 layer to crack. For a Ti capping layer, a strong increase of the thermal stability of the CoSi2 layer is observed, even if the Ti capping layer is removed by a selective etching step after the first RTP annealing. The presence of a very thin Ti-O-N containing layer on the CoSi2surface seems to strongly decrease surface diffusion and in this way reduce the tendency for grain boundary grooving.

ZrO2 and HfO2 and their alloys with SiO2 are currently among the leading high-k materials for replacing SiOxNy as the gate dielectric for the sub-100 nm technology nodes. International SEMATECH (ISMT) is currently investigating integration issues associated with this required change in materials. Our work has focused on the integration of ALCVD deposited ZrO2 and HfO2 with an industry standard conventional MOSFET process flow with poly-Si electrode. Since the impact of contamination by these new high-k materials introduced in a production fab has not yet been established, it becomes very critical to prevent cross- contamination through the process tools in the fab. A baseline study was completed within ISMT's fab and appropriate protocols for handling high-k materials have been established. The integrated high-k gate stack in a conventional transistor flow should not only meet all the performance requirements of scaled transistors, but the gate dielectric film should be able withstand high-temperature anneal steps. Reactions between ZrO2 and Si have been observed at temperatures as low as 560°C (during the amorphous Si deposition process). Various wet chemistries were also evaluated for removing the high-k film inadvertently deposited on wafer backside, and it was found that ZrO2 etches at extremely slow rates in the majority of the common wet etch chemistries available in a fab. A new hot HF based process was found to be successful in lowering Zr contamination on the wafer backside to as low as 1.8 E10 atoms/cm2. The patterning of a high-k gate stack with poly-Si electrode is another area that required considerable focus. Various dry (plasma) etch and wet etch chemistries were evaluated for etching ZrO2 using both blanket films as well as wafers with patterned poly-Si gate over the high-k films. On the full CMOS flow device wafers, most of these wet chemistries resulted in severe pitting in the ZrO2 film remaining over the source/drain (S/D) areas, as well as in the Si substrate and the field oxide. A poly-Si gate over ZrO2 gate dielectric film was successfully patterned using the standard poly-Si gate etch (Cl2/HBr) for the main etch, followed by a combination of HF and H2SO4 clean for removing all of the ZrO2 remaining over the S/D area. This allowed the fabrication of low-resistance contacts to transistor S/D areas, which ultimately resulted in demonstration of functional transistors with high-k gate dielectric films.

When a Ta layer is deposited at the Si/Ti interface a new phase has been detected, i.e. theTiSi2C40. The C40-C54 transformation kinetics and the film morphology are consistent with an increase of the nucleation density with respect to the C49-C54 transition. The activation energies for the nucleation rate (4.2±0.3 eV) and the growth velocity (4.0±0.4 eV) have been obtained from the in situ sheet resistance and the Transmission Electron Microscopy results. These results show that the process with a Ta layer at the Ti/Si interface has a greater scalability with respect to the standard TiSi2 process.

This letter describes a unique process for the preparation of high quality tantalum oxynitride (TaOxNy) with zirconium silicate (ZrSixOy) as an interfacial layer for use in gate dielectric applications. Compared with conventional native silicon oxide and oxynitride as an interfacial layer, tantalum oxynitride (TaOxNy) MOS capacitors using zirconium silicate (ZrSixOy) as an interfacial layer exhibit lower leakage current levels at the same equivalent oxide thickness. We were able to confirm TaOxNy/ZrSixOy stack structure by auger electron spectroscopy (AES) and transmission electron microscope (TEM) analysis. The estimated dielectric constant of TaOxNy and ZrSixOywere approximately 67 and 7, respectively. The zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications.

We investigated the electrical characteristics of the MOSCAP structures with W/WNx/poly Si1−xGex gates stack using C-V and I-V. The low frequency C-V measurements demonstrated that the flat band voltage of the W/WNx /poly Si0.4Ge0.6 stack was lower than that of W/ WNx /poly Si0.2Ge0.8 stack by 0.3V, and showed less gate-poly-depletion-effect than that of W/ WNx /poly- Si0.2Ge0.8 gates due to the increase of dopant activation rate with the increase of Ge content in the poly Si1−xGex films. As Ge content in poly Si1−xGex increased, the leakage current level increased a little due to the increase of direct tunneling and QBD became higher due to the lower boron penetration.