Detecting impurities or contaminations in the ultra thin silicon oxide layer is one of the most serious challenges in wafer processing as device is scaled down toward deep sub-micron. These impurities or contaminations will create charge traps in the oxide layer and degrade gate oxide integrity (GOI). The MOS Capacitance-Voltage method which has been used to study the electrical charges in relative thicker oxide layer (> 5 nm) cannot detect, however, these contaminations related charges in the ultra thin silicon oxide layer. In this article, a new method has been developed to determine the electrical charges associated with the contaminations in an ultra thin oxide layer using Hg-Schottky capacitance-voltage method. The oxide layers of 1.2 nm in thickness with and without Cu-contamination have been tested with this new method. The results show that the new method can be used to qualitatively identify the electrical charges trapped in the ultra thin silicon oxide layer and the trapping levels associated with the contamination. The interactions among sub-stochiometric oxide structure and electron traps introduced by the metal impurities have been discussed.

We have obtained an analytic solution of linear elasticity for the stress distribution under a thin film edge in isotropic substrates of finite thickness and of infinite extent in the other two directions. The following boundary conditions are considered. At the film/substrate interface and the free surfaces at the top and bottom of the substrate, the normal stress component vanishes. Far from the film edge on the side without the film, all stress components are zero. Far from the film edge under the film, the stress distribution is in accordance with that given by the bimetallic strip theory. Two examples of comparison between theory and experiments were given to demonstrate the validity of this solution. The infrared photoelastic stress fringe pattern obtained by a dark-field plane polariscope in a Si substrate under an oxide film edge was successfully reproduced. The calculated and experimental results of Raman-shift of Si under patterned CoSi2 line structures also showed good agreement with each other.

We have incorporated several percent of nitrogen only near the top surfaces of thermally grown oxides by exposure to fluorine gas at room temperature followed by an atomic nitrogen treatment at 550°C. The depth profiles and the bonding of incorporated nitrogen atoms have been studied by angle-resolved x-ray photoelectron spectroscopy.

MOS devices were fabricated using the nitrided oxide with boron doped polycrystalline silicon gate. From the capacitance-voltage measurements we confirmed that the nitrided oxide would prevent the boron penetration in comparison with the conventional oxide films. The proposed technique identifies a unique process for obtaining high quality ultrathin dielectrics.

Continued scaling of CMOS technology beyond the 100 nm technology node will rely on fundamental changes in transistor gate stack materials [1]. Refractory metals and their metallic derivatives are among the only candidates suitable for use as transistor gate electrodes. In earlier publications, Mo has been proposed as a potential candidate for use as a MOSFET gate electrode and the implantation of nitrogen ions into the Mo film has been observed to lower the interfacial work function of Mo [2,3]. This observation indicates the potential application of Mo as a CMOS gate electrode. In this paper, the dependence of the interfacial work function on the nitrogen implant parameters (viz. energy and dose) is discussed. In general, metal work functions at dielectric interfaces depend on the permittivity of the dielectric [3,4,5]. This dependence of the gate work function on dielectric permittivity presents a significant challenge for the integration of metal gate electrodes into future CMOS technology. In light of this, the ability to engineer the Mo gate work function over a relatively large range makes it an attractive candidate for this application.

In this paper, the effect of pre-cooling treatment on the low resistivity C54 phase titanium silicide film growth was investigated. Our experimental results and micro-structural analysis show that, by introducing such cooling treatment into the titanium silicide process to precede the conventional rapid thermal annealing, the low resistivity C54 phase formation can be enhanced. Defects at the Si/Ti interface caused by the thermal mismatch between titanium and silicon layers during the cooling treatment were found to contribute to the increase of the C49 nucleus sites. This help to supply more C49 grain boundaries and triple junction sites at which the C54 phase could nucleate. This discovery has the potential to reduce the complexity and cost associated with forming low resistivity titanium silicide on sub-micron structures for future ULSI application.

Ti-Si-O films were sputter deposited from TiO2+SiO2 composite targets with various SiO2 content. The phase separation occurred for every SiO2 content used in this experiment (from 14% to 75%) and it has been revealed that nanocrystalline (TiO2)1-x(SiO2)x films in which anatase TiO2 forms tiny grains were obtained when x in the film is larger than 0.26. The tiny grain was effective for suppressing the thermal grooving phenomenon of the thin films by the post deposition annealing which leads to the leakage current increase. The dielectric constant of the nanocrystalline film was varied with the SiO2 content from the value of the bulk anatase to SiO2.

Rapid shrinking in device dimensions calls for replacement of SiO2 by new gate insulators in future generations of MOSFETs. Among many desirable properties, potential candidates must have a higher dielectric constant, low leakage current, and thermal stability against reaction or diffusion to ensure sharp interfaces with both the substrate Si and the gate metal (or poly-Si). Extensive characterization of such materials in thin-film form is crucial not only for selection of the alternative gate dielectrics and processes, but also for development of appropriate metrology of the high-k films on Si. This paper will report recent results on structural and compositional properties of thin film SrTiO3 and transition metal oxides (ZrO2and HfO2).

The electrical performance of transistors built using thin films of the column IVB metal oxides ZrO2 and HfO2 deposited from their respective anhydrous metal nitrate precursors is presented. In contrast to earlier work on TiO2, which is thermodynamically unstable on silicon, ZrO2 and HfO2 form well-defined oxynitride interfacial layers and have a good interface with silicon with much less fixed charge. The inversion layer mobility for an HfO2 / SiOxNy / Si stack is comparable to that of a conventional SiOxNy/Si interface.

This paper reports the dependence on the concentration of the germanium (Ge) in polycrystalline silicon (poly-Si) cap layer on the polycrystalline silicon germanium (poly-SiGe) for low resistivity cobalt disilicide (CoSi2) formation. Particularly, we investigate the relationship between sheet resistance of CoSi2 films and concentration of Ge in cap-Si layer. The excellent value of sheet resistance (∼6 / ) is achieved by Ge concentration in cap-Si layer controlled at 2% or less for 90nm length CoSi2/poly-Si/poly-SiGe gate structure. This result indicates that conventional Co silicide process technology can be readily used even for poly-SiGe gate structure.

NiSi formation is known to be hindered by interfacial native oxide. Such oxide is easily formed on the Si surface through inefficient cleaning or a long time lag prior to Ni deposition. In this study, two methodologies were investigated to remove this layer of native oxide when no DHF clean was performed prior to metal deposition. Firstly, the deposition of a 100°C Ti cap layer after Ni deposition and secondly, the deposition of a middle 50Å Ti prior to Ni deposition. The samples were then rapid thermal annealed from 500 to 800°C. It was found for the Ti / Ni / SiO2 / Si stack, a layer of NiSi was formed starting from 600°C. Transformation to the NiSi2 phase begins at 750°C. As for the Ni / Ti / SiO2 / Si stack, a layer of NiSi was formed after 500°C annealing and conversion to NiSi2 also took place at 750°C. However, it was found that at low temperatures such as 500-600°C, facets of NiSi2 were identified under the thick NiSi layers, embedded in the Si substrate. Ternary phases like TixNiySiz were also identified at the surface of the sample.

The silicidation reactions and thermal stability of Co silicide formed from Co-Ta/Si systems have been investigated. In case of Co-Ta alloy process, the formation of low resistive CoSi2phase is delayed to about 660°C, as compared to conventional Co/Si system. Moreover, the presence of Ta in Co-Ta alloy films reduces the silicidation reaction rate, resulting in the strong preferential orientation in CoSi2 films. Upon high temperature post annealing in the furnace, the sheet resistance of Co-silicide formed from Co/Si systems increases significantly, while that of Co-Ta/Si systems maintains low. This is due to the formation of TaSi2 at the grain boundaries and surface of Co-silicide films, which prevents the grain boundary migration thereby slowing the agglomeration. Therefore, from our research, increased thermal stability of Co-silicide films was successfully obtained from Co-Ta alloy process.

In this paper we report the growth of thin titanium oxide films on Si (100) and quartz at low temperatures (≤350°C) by photo-induced chemical vapor deposition (photo-CVD) with 222 nm UV radiation using a novel injection liquid source, which overcomes the reproducible problem in conventional bubblers. The properties of the films formed have been studied using ellipsometry, UV spectrophotometry and Fourier transform infrared spectroscopy (FTIR) measurements. Nanostructured films were observed by atomic force microscopy (AFM). It was found that crystalline TiO2 films could be formed at deposition temperatures as low as 210°C by x-ray di ffraction (XRD). The influence of the deposition temperature on the film is discussed. The refractive index as high as 2.5 can be obtained at a deposition temperature of 350°C, while an optical transmittance of between 80-95% in the visible region of the spectrum was obtained at different deposition temperatures. Physical and optical characterization both reveal good film qualities, rendering this technique promising for a wide range of industrial application in low temperature microelectronic and optoelectronic material processing as well as for many heat sensitive compounds.

In this paper, we have reported an attempt to decrease equivalent oxide thickness (EOT) of TiO2gate insulator by thinning the amorphous layer formed at the TiO2/Si interface. We have decreased the thickness of the TiO2/Si interfacial layer to as little as 1.6 nm by suppressing the oxygen flow rate during the TiO2 sputtering. It was confirmed that the dielectric constant of the interfacial layer revealed higher value than that of SiO2, depending on the sputtering condition. Titanium in the interfacial layer, which was responsible for the polarization enhancement, was explicitly identified by high spatial resolution TEM-EELS. As a result, EOT of 1.3 nm was realized by TiO2/Ti-Si-O stacked gate insulator without any degradation in the electrical characteristics.

Continued scaling of device dimensions requires deposition of high-quality thin films with a thickness of 50 angstroms or less. Nucleation effects in typical CVD processes make it difficult to achieve continuous films in this thickness regime. Atomic layer deposition (ALD), a technique developed over 25 years ago but applied to IC processing only recently, enables deposition of ultra-thin films with atomic-scale precision. This technique offers 100 percent step coverage of high aspect ratio features, as-deposited films which are amorphous and free of pinholes, excellent within-wafer uniformity and wafer-to-wafer uniformity, and favorable electrical properties. Moreover, ALD offers the opportunity to engineer material properties by creating layered structures (nanolaminates) and mixtures (alloys) which combine advantageous properties of different materials. These last features may be critical in efforts to replace silicon dioxide as the industry's dielectric workhorse if no single material emerges as a suitable direct replacement. The nanolaminate capability of ALD will be discussed with physical and electrical data on nanolaminates of aluminum oxide with tantalum pentoxide and aluminum oxide with hafnium oxide. Individual nanolaminate layers can be varied from tens of angstroms to as little as 1-2 atomic layers. Data for Al2O3/Ta2O5 and Al2O3/HfO2 alloys will also be presented demonstrating the ability to create materials with controlled, variable composition. The alloy and nanolaminate capabilities enable the creation of graded interfaces and atomically smooth transitions between different materials. Prospects for application of these materials to gate stacks and capacitors will be assessed.

Current high permittivity material deposition techniques produce a low permittivity oxide interfacial layer consequently increasing the equivalent oxide thickness. This interfacial oxide layer can be prevented by initially growing a thin nitride layer to act as a diffusion barrier. The interfacial nitride layer must also have low interface state densities comparable to state-of-the-art SiO2 insulators in order to be suitable for MOSFETs. The nitride layer used in this study was formed by thermal nitridation in a UHV system, with the subsequent high permittivity deposition done in an adjoining system. After forming capacitors from these films, capacitance vs. voltage (C-V) techniques were used to determine the interface state density and equivalent oxide thickness of the films. Gate stack films were produced on Si(100) and Si(111) and the results are compared. Gate stacks on Si(100) show a slight increase in stretchout in the high frequency C-V curves for both n-type and p-type samples. Initial data suggests that Si(111) has a lower interface state density than the Si(100) gate stacks. This may be attributed to the Si3N4layer on Si(111) being epitaxial nitride.

A new process was developed for deposition of the silicates and oxides of metals such as zirconium and hafnium at low substrate temperatures (100–300°C). The silicon and oxygen source is tris(tert-butoxy)silanol, (tBuO)3SiOH, and the metal precursors are metal amides. A typical reaction is

ZrL4 + 2 (tBuO)3SiOH → ZrSi2O6 + 4HL + 6H2C=C(CH3)2 + 2 H2O

in which the ligand L is ethylmethylamide, -NEtMe. The precursor vapors were alternately pulsed into a heated reactor, yielding about 0.3 to 0.7 nm of metal silicate film for each cycle. Replacing the silanol pulses with water pulses yields pure metal oxides with a thickness of about 0.1 to 0.15 nm per cycle. The silicon content of the films can be adjusted to any desired value by replacing some of the silanol pulses by water pulses. This new process has a number of advantages over previous methods for depositing metal silicates. Uniformity of thickness and stoichiometry are readily achieved. The deposition atmosphere is non-oxidizing, so that formation of low-k interfacial oxides between the deposited layer and a silicon substrate is minimized. The new halogen-free precursors avoid halogen contamination of films and corrosion of deposition systems. This process is a promising method for forming the next generation of ultra-thin high-k gate dielectrics in silicon-based microelectronics.

Thermal stability of nickel silicide is improved by adding a thin Co interlayer at Ni/Si interface. After high temperature anneal, the low sheet resistance of silicide and the low junction leakage of the ultra-shallow junction show the lack of film degradation. The transformation to disilicide phase occurred at a lower temperature. At 850°C, interface shows the truncated facet structure extended 100° to 200° below silicide/Si interface. With Co addition, nickel silicide formed on polysilicon and on SiGe films also show improved thermal stability and low sheet resistance. Formation temperature of disilicide phase occurred at lower temperature in all these cases.

The silicide formation for Ni/Pd and Pd/Ni bilayers on Si(100) substrates was investigated. X-ray diffraction and photoelectron spectroscopy (XPS) depth profiling have been applied to study the phase formation of the silicide. We found that with addition of Pd into Ni/Si, a uniform layer of ternary Ni1−xPdxSi layer formed and kept stable for a wide temperature range. The lattice parameter of Ni1−xPdxSi as a function of Pd addition was calculated. The nucleation temperature of NiSi2 was delayed due to the addition of Pd. The higher the Pd addition, the larger the increase in NiSi2 nucleation temperature. We also studied the effect on the addition of Ni to the Pd/Si reaction. For pure Pd/Si reaction PdSi nucleated from Pd2Si at 750°C or above. For Ni/Pd/Si reaction, Pd2Si changed to Ni1−xPdxSi at temperature lower than 750°C due to the incorporation of Ni. The phenomena were explained by classic nucleation theory taking into account the effect of mixing entropy effect.