Analysis of the National Technology Roadmap for Semiconductors (SIA) indicates a potential crisis in performance and reliability regarding the scaling of interconnects. In the future, increased component density and performance (e.g. logic instructions / sec.) may not be able to be achieved simultaneously for technology generations well before the manufacture of 0.1μm feature sizes circa 2005. Thermal management and engineering of signal noise are key issues. Although much can be done to achieve higher speed with product design architecture, one must consider new material paradigms by 0. 1μm generation to address the RC crisis.

Needs exist in low cost simplified processes across a broad area of applications: local salicide interconnects, lower process temperature for poly-metal dielectric (to enable shallower junctions), lower dielectric constant materials for interconnects, and robust barriers for interconnect plugs and wiring metals. A shift to lower dielectric constant (low-k) materials (e.g. SiO-F, polymers, or aerogels) will be used as soon as integrated processes are demonstrated and manufacturing tools become available. The next full generation window of opportunity is the 0.18um generation (1GB) scheduled for manufacturing prototyping in 1998.

This paper reviews the overall Roadmap characteristics, major solution strategies, and outlines the challenges in design, technology, and integration for 0.18μm and 0.1μm generations. Topics reviewed include discussion of process architectures and electrical characterization methodologies. Among the most challenging areas we have: control and lowering of contact resistance, manufacturing interconnects at aspect ratios exceeding 4:1, use of very low dielectric constant materials in multilevel counts approaching 6–7, use of controllable ultra thin barrier materials for interconnect plugs and wiring, barriers and cladding for containment and passivation of Cu, development of manufacturing worthy selective processes, engineering stress/electromigration issues and thermal management of low-k dielectric systems. New materials must be introduced into existing technology frameworks while designs migrate to lower voltage operation.

It is clear that, at the device level, CMOS is scaleable to 0.1 μm and beyond, provided that the power supply voltage and the device physical dimensions are reduced in some coordinated manner. Contacting these devices and connecting them into circuits, and wiring the circuits at the chip level will become ever more challenging. Furthermore, the integration level of 0.1-μm technology is such that the chip will be the system or at least the core of the system. Thus, the BEOL will not be just for interconnecting the circuits on the chip, but provide the interconnect functions that are presently on the package and/or the board. To this end, copper and low-ε inter-level dielectric, on-chip decoupling capacitor, as well as wire-level hierarchy, will be needed.

Based on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. The distribution is then used to describe an optimal architecture for a multilevel wiring network that provides maximum interconnect density and minimum chip size for a ULSI system. In addition, this new distribution has been incorporated into a Generic System Simulator (GENESYS), that projects overall performance of future ULSI systems. Assuming various interconnect materials such as copper, aluminum, silicon dioxide, and low dielectric polymers, GENESYS has been used to examine the effects that each material has on overall performance of ASIC's over the next 15 years.

We describe how x-ray microbeam diffraction is being used to measure strain with micronscale spatial resolution. Micron-scale x-ray beams can be obtained using tapered glass capillaries. With the high brightness and broad energy spectrum of synchrotron radiation and the energy dispersive capabilities of commercially available, liquid nitrogen cooled x-ray detectors, spatially resolved strains in a sample can be determined along different directions without having to rotate the sample, in contrast with more conventional methods using monochromatic x-ray diffraction. This is a major advantage in achieving micron-scale spatial resolution. Strain sensitivities on the order of 2×10−4 have been achieved in such measurements. White beam x-ray microdiffraction has been applied for the first time in real-time studies of thermal and electromigration related strain distributions in passivated Al-on-Si conductor lines. Results of measurements on a single 10μm-wide line are described.

The local mechanical stress induced in a silicon substrate by silicide lines (CoSi2, CoSi, C49 and C54 TiSi2) with different thicknesses, widths and spacings is studied using micro-Raman spectroscopy. The results show that the stress becomes larger with increasing line thickness and decreasing line spacing. For the different silicides, the stress increases according to: CoSi < CoSi2 < C49 TiSi2 < C54 TiSi2. By fitting a simple stress model to the Raman data, quantitative values for the stress components can be determined. The dependence of the TiSi2 phase on thickness and line width is studied for the same samples. These studies show that micro-Raman spectroscopy can provide local information (μm resolution) on the TiSi2 phase.

Preferential crystal orientation of low-resistance C54 TiSi2 formed in the reaction of polycrystalline and single crystal silicon with titanium was investigated for Ti thicknesses ranging from 15 to 44 nm. Using in situ synchrotron x-ray diffraction during heating of 15 nm of Ti on single crystal Si, we observed that the C54 TiSi2 silicide film showed predominantly <040> grains oriented normal to the sample. In thicker silicide films the <311> orientation dominated or film was randomly oriented. An ex situ four circle diffractometer was used to investigate the strong <040> texture in narrow line arrays of C54-TiSi2 formed on polycrystalline silicon with linewidths from 0.2 to 1.1 μm. We observed that the angular distribution of <040> Ti Si2 grains is dependent on the line direction, where the majority of grains had their (100) planes oriented parallel with the line direction. These findings support a model of the C49 to C54 TiSi2 transformation involving rapid growth of certain orientations favored by the one-dimensional geometry imposed by narrow lines.

We present a study of the quantum well states observed in Cu/Ni(001). Several reports in the recent past have shown that these states, which are derived from the bulk, disperse through the Fermi level at a thickness of about 6 ML. Using angle-resolved photoemission, we have imaged the photoelectron angular distributions from several thicknesses of Cu/Ni(001). We observe that these states have s,p like symmetry and are located near the zone edge.

Two Fe/Gd/Fe/Gd multilayers with different layer thicknesses were grown on Si (100) by magnetron sputtering. The as-deposited samples were vacuum-annealed at 100°C, 200°C, and 300°C. They were studied by grazing incidence x-ray diffraction (XRD), secondary ion mass spectroscopy (SIMS), vibrating sample magnetometer (VSM) and magneto-optical Kerr effect (MOKE). The deposition rates for Fe and for Gd are (1-2) and 4 Å s−1, respectively. The XRD and SIMS data show that interdiffusion occurs between Fe and Gd layers, and between Gd and Si layers. The thicker multilayers show strong in-plane uniaxial anisotropy.

Electromigration in metals is due to microscopic forces acting on mobile defects. These microscopic forces arise from the local electric field that accompanies electron transport, and the resulting defect migration is a consequence of the dynamic response of the defect to this local field. Theoretical results are given for the local electric field and the electromigration driving force on impurities in bulk systems and in metallic microstructures where surfaces, grain boundaries and dislocations play an important role. Extensions of the theory are described for mesoscopic systems, and local heating is shown to be an important effect as the size of the system becomes smaller and the electron current is larger.

Copper stripes, current stressed under UHV, clean surface conditions, have an activation energy Q for electromigration (EM) of 0.5 eV, significantly lower than the 0.8 eV reported when the surface has been exposed to air. Application of positive or negative potentials to the stripes during EM testing raises or lowers the clean surface Q in a linear relationship in the range of 0.2 to 1.0 eV. These results were obtained from in-situ electrical resistance measurements during which potentials up to +/− 800 volts were applied to the stripe. Thus the rate at which surface EM takes place is influenced by the sign and magnitude of the applied potential. The low Q for the in-situ clean surface studies also implies that surface diffusion is the dominant physical mechanism whereby EM damage occurs. Ex-situ SEM studies support this conclusion. This work has important implications for ULSI since numerous recent studies have indicated that surface and/or interface diffusion are present during current stressing of passivated and unpassivated fine line stripes.

Atom movements of Cu in pure Cu and Cu(0.5 to 2 wt.% Sn) alloys have been investigated using drift velocity and radioactive tracer techniques. The void growth rate in pure Cu at the cathode end, as a result of electromigration driving force, linearly increases with the applied current density. A marked decrease in the Cu grain boundary diffusivity and electromigration drift velocity is attributed to Sn trapping of Cu atoms and/or binding defects at grain boundaries. The effect is more pronounced at lower temperatures. The activation energies for electromigration and diffusion of Cu in pure Cu grain boundaries were found to be in the range of 0.7 - 0.9 eV. Addition of about 0.5 to 2 wt.% Sn increased these energies to 1.1 - 1.3 eV, respectively which resulted in enhancement of electromigration resistance by several orders of magnitude over that in pure Cu at the field operation temperature.

In narrow metal lines used for chip level interconnects, the line width can strongly affect the electromigration reliability, typically due to variations in the microstructure and in the mechanical stress state. These variations have a stronger effect as the line width decreases to the order of the metal grain size or less. Electromigration failure distributions were obtained both experimentally and by simulation for realistic interconnect structures with six different line widths, ranging from lμm to 8μm. In order to simulate the electromigration failure distributions, microstructure statistics were obtained (using TEM) and the critical void volume for failure was measured (using SEM) for each line width. The simulated failure times match the experimental failure times for narrow line widths (1-4μm).

Electromigration (EM), the mass transport phenomenon under applied electrical field, is known to cause degradation in interconnections and thus to compromise the devices' reliability. High current density and high temperature conditions are usually adopted to evaluate the EM lifetime. Such high current density will raise the temperature at the test sites because of Joule heating. Thus the actual temperature on the test surface, not the ambient temperature, is an important parameter affecting the lifetime of the metallization. A simple model is proposed here to predict the temperature rise in such interconnections and the calculated values agree well with the experimentally measured rise in temperature. Only heat conduction and convection are considered and illustrative equivalent electrical analogy technique is used to solve the problem. This model, using a commercially available spreadsheet and its iteration functions, is shown to match closely with experimental results.

Activation energy of electromigration damage was determined as 1.2 eV for Cu lines, indicating grain boundary paths for electromigration. The surface diffusion was found to play a role during electromigration in Cu and impeded the failure process.

Copper films were deposited onto oxidized silicon wafers by the self-ion assisted technique. A 0 and 6 kV bias was applied to the substrate during the deposition. The films were patterned into parallel line arrays of 20 lines 0.5 mm long, using electron lithography and dry etching. After patterning, the lines were covered by silicon oxide and annealed in vacuum for 1 hour at the temperature 450° C. Electromigration testing was performed in air in the temperature range from 280° to 350° C and at a current density 3.106 A/cm2.

It was found that the resistivities of the films deposited at 6 kV and without bias were 1.7 and 2.0 μΩcm, respectively. The median times to failure are 398.6 and 240 h and the deviations in the time to failure are 0.8 and 0.54 for 6 kV lines and 0 kV lines, respectively. An electromigration activation energy of 0.89 eV was found for 0 kV films.

The interdiffusion of Cu and Sn and the formation and dissolution of Cu-Sn precipitate phases have been examined for Cu(Sn) alloy thin films. Cu(Sn) films were deposited by electron beam evaporation in either a Sn/Cu bilayer or Cu/Sn/Cu trilayer film structure, with overall Sn concentrations from 0.1 to 5 atomic percent. Analysis by in situ resistivity, calorimetry, electron diffraction and x-ray diffraction measurements indicates that the bilayer and trilayer films form the intermetallic phase η-Cu6 Sn5 during film deposition. Upon heating, the ε-Cu3Sn phase forms at 170°C, then this phase dissolves into the Cu matrix at approximately 350°C. Finally, ζ- Cu10Sn3 phase forms and precipitates after heating to 500°C and cooling to room temperature. The final resistivity of Cu/Sn/Cu films with more than 2 atomic percent Sn was greater than 3.5 μΩ - cm. However, resistivities from 1.9 to 2.5 μΩ - cm after annealing were obtained with Cu/Sn/Cu films containing less than 2 atomic percent Sn.

CuCr alloys with varying Cr content were sputter deposited on polyimide films, and the metal/polyimide films were maintained under 350°C/N2 environment up to 10 hours for reliability measurements. Before exposure to 350°C, the peel strength increased proportionally with the Cr content in the alloy layer up to 17% and saturated. After exposure to 350°C, the peel strength dropped for all the specimens due to the formation of Cr2O3 at the metal/polyimide interface, and the effect was most drastic for the specimen with the lowest Cr content, which failed along the Cr-oxide/polyimide interface. Depletion of carbidic bonds at the metal/polyimide interface accompanied the oxide formation, and the result was quite devastating for the specimens with low Cr content in the alloy layer.

The continual trend in decreasing the dimensions of semiconductor devices results in a number of technological problems. One of the more significant of these is the increase in contact resistance, Rc. In order to understand and counteract this increase, Rc needs to be quantitatively modelled as a function of the geometrical and material properties of the contact. However the use of multiple semiconductor layers for ohmic contacts makes the modelling and calculation of Rc a more difficult problem. In this paper, a Tri-Layer Transmission Line Model (TLTLM) is used to analyse a MOSFET ohmic contact and gatedrain region. A quantitative assessment of the influence on Rc of important contact parameters such as the metal-silicide specific contact resistance, the silicide-silicon specific contact resistance and the gate-drain length can thus be made. The paper further describes some of the problems that may be encountered in defining Rc when the dimensions of certain types of contact found in planar devices decrease.

A new formation method for an ultra-low resistivity contact and structural analysis are discussed. In this study, a minimum contact resistivity of 6.9× 10−9 Ω·cm2 has been successfully obtained in an AlSi(lwt%)Cu(0.5wt%) alloy / Si system by using heavy dose ion implantations of Ge and B combined with low temperature annealing as low as 550°C. Structural analysis on the Si surface layer has been carried out. As a result, it was found that the crystal lattice was expanded in-plane by 6% in the Si layer near the surface because of the high concentration of Ge and no relaxation of lattice strain at such a low temperature. It was also found that super-saturation of B was stably formed in this system. An ultra-low resistivity contact is considered to be a result of these combined effects.

We propose a new systematical method to control Schottky barrier heights of metal/semiconductor interfaces by controlling the density of interface electronic states and the number of charges in the states. The density of interface states is controlled by changing the density of surface electronic states, which is controlled by surface hydrogenation and flattening the surface atomically. We apply establishing hydrogen termination techniques using a chemical solution, pH controlled buffered HF or hot water. Also, slow oxidation by oxygen gas was used to flatten resultant semiconductor surfaces. The density of interface charges is changeable by controlling a metal work function. When the density of surface states is reduced enough to unpin the Fermi level, the barrier height is determined simply by the difference between the work function of a metal φm and the flat-band semiconductor ØsFB. In such an interface with the low density of interface states, an Ohmic contact with a zero barrier height is formed when we select a metal with φm < φsFB. We have already demonstrated controlling Schottky and Ohmic properties by changing the pinning degree on silicon carbide (0001) surfaces. Further, on an atomically-flat Si(111) surface with monohydride termination, we have observed the lowering of an Al barrier height.