In this paper, a detailed reliability investigation is presented for ultra-thin tunneling (∼50 Å) oxides grown in N2O ambient using rapid thermal processing (RTP). These N2Oss-oxides are compared with oxides of identical thickness grown in O2 ambient by RTP. The reliability investigations include time-dependent dielectric breakdown as well as stress-induced leakage current in MOS capacitors with these gate dielectrics. Results show that ultra-thin N2O-oxides show much improved reliability as compared to oxide grown in O2 ambient.

Proximity rapid thermal diffusion is presented as a doping process for fabrication of very shallow junctions. The kinetics of Si doping with B, P and As is investigated using sheet resistance measurements, secondary ion mass spectroscopy and FTIR analyses. The efficiency of doping is affected by the dopant transport in the SOD which depends on the structure and composition of the SOD.

As device performance requirements increase, device features become smaller and films become thinner. The resultant sensitivity to defect density is such that controlling the condition of wafer surfaces prior to primary process steps becomes more and more critical. Wafer cleaning technologies of the past may not be optimum in providing needed device characteristics and reliability of tomorrow's semiconductors. In this paper, we compare the currently used RCA wafer clean chemistries to newer HF last, vapor dry technologies which use direct displacement of liquids to minimize contaminants. Subsequent passivation of these hydrophobic wafer surfaces is accomplished by various methods of oxidation including chemical treatments and RTP processing. Data collected from I-V, SIMS and DEFECT DENSITY testing will be included in the presentation.

The feasibility of using isothermal RTA in annealing ion implanted layers for forming junctions has been investigated for the past 10 years. While many of the scientific details surrounding defect formation, transient diffusion and dopant activation remain to be clarified, RTA intrinsically is a viable annealing process which is essential for fabricating advanced silicon devices.

SiO2 thin films were deposited by remote PECVD on Si surfaces exposed to species generated in O2/N2 and O2/NH3 plasmas. The surface chemistry was studied by Auger Electron Spectroscopy, AES, and the electrical properties of the SiO2/Si interface by high frequency and quasi-static Capacitance-Voltage, C-V, measurements. The AES results showed that Ccontamination was removed by exposure to both plasma-excited gas mixtures, but that N-atoms were incorporated into the SiO2 film, and Si-N bonds were formed at the SiO2/Si interface. C-V measurements indicated that the Si-N bonding structure, rather than the N-atom concentration, is critical in determining the interface electrical properties. The effects of Rapid Thermal Annealing, RTA, on the electrical properties of these SiO2/Si interfaces were also studied.

Process modules for MOS gate fabrication were developed which can be completed subsequently in one RTP reactor: atmospheric process sequences for gate oxides and oxynitrides as well as low pressure chemical vapor deposition of polysilicon (RTCVD). Prior to the Rapid Thermal Oxidation (RTO), the wafers were treated with a Rapid Thermal Cleaning process (RTC) in H2/Ar ambient. After the desoxidation step the RTO was done in O2/H2/Ar followed by an anneal (RTA) for the gate oxide or a nitridation in NH3 (RTN) and reoxidation for the oxynitrides, respectively. The polysilicon gate electrode was fabricated either by RTCVD in situ or in a conventional furnace reactor. The two-step RTCVD process resulted in a very good thickness uniformity for the polysilicon layers of 3% (3mm from the edge). The influence of the process variations on breakdown field, fixed oxide charge, interface state density, flatband voltage, and threshold voltage of the different types of gate dielectrics was investigated. The charges and voltages were determined by LF-HF CV measurements. In order to characterize the radiation tolerance of electronic devices, radiation induced flatband and threshold voltage shifts as well as the build up of interface charges were determined. The irradiation was performed at a Co - 60 gamma source. Breakdown fields in the range of 19 MV/cm, interface state densities of less than 109 eV−2cm−2, and radiation induced threshold voltage shifts below 0.1 V after 1.5 Mrad(Si) were obtained.

A combination of i) low-temperature, 300-400°C, plasma-assisted oxidation to form the SiO2/Si interfaces, and ii) 800°C rapid thermal chemical vapor deposition, RTCVD, to deposit SiO2 thin films have been used to fabricate gate-oxide heterostructures. This sequence separates SiO2/Si interface formation by the oxidation process from the deposition of the bulk oxide layer by RTCVD. These two processes were performed in situ and sequentially in a single-chamber, ultraclean quartz reactor system. We have studied the chemistry of the interface formation process by Auger electron spectroscopy, AES, and the electrical properties of MOS devices with Al electrodes by C-V techniques.

Strained-layer semiconductors have revolutionized modern heterostructure devices by exploiting the modification of semiconductor band structure associated with the coherent strain of lattice-mismatched heteroepitaxy. The modified band structure improves transport of holes in heterostructures and enhances the operation of semiconductor lasers. Strainedlayer epitaxy also can create materials whose band gaps match wavelengths (e. g. 1.06 μm and 1.32 μm) not attainable in ternary epitaxial systems lattice matched to binary substrates. Other benefits arise from metallurgical effects of modulated strain fields on dislocations.

Lattice mismatched epitaxial layers that exceed the limits of equilibrium thermodynamics will degrade under sufficient thermal processing by converting the as-grown coherent epitaxy into a network of strain-relieving dislocations. After presenting the effects of strain on band structure, we describe the stability criterion for rapid-thermal processing of strained-layer structures and the effects of exceeding the thermodynamic limits. Finally, device results are reviewed for structures that benefit from high temperature processing of strained-layer superlattices.

Rapid thermal annealing (RTA) has been employed for the electrical activation of shallow n-channel layer by Si+ implantation in the fabrication of GaAs MESFET. To prevent considerable outdiffusion of gallium and arsenic from GaAs substrate during annealing, encapsulating layers such as SiNx and SiNx/SiO2 are deposited. The SiNx/SiO2 double dielectric encapsulant is shown to be more effective to improve the electrical activation. Depending on RTA temperature between 900 and 950°C, the maximum activation efficiency exhibits 77% at the implanted energy of 70 keV and the dose of 5x1012 cm−2. SIMS analyses show the reduction of the hydrogen contained in the silicon nitride and no outdiffusion of Ga and As during RTA. It also shows the sharp Si-profile after RTA at 950°C, 30 sec. The MESFET fabricated using activation with RTA provides better transconductance than that with furnace-annealed activation.

An improved technique for impurity/defect passivation of silicon solar cells is described. A low-energy hydrogen implantation is performed from the back side of solar cells to produce a deep hydrogen diffusion. The deep diffusion is believed to be caused by the formation of a mobile hydrogen-vacancy (H-V) complex. Next, a layer of Al is deposited on the hydrogenated side and an Optical Processing (OP) step is performed. The OP step accomplishes several objectives that include formation of an ohmic contact, dissociation of H-V complexes to release hydrogen that can participate in further passivation, and dissolution and regrowth of the highly defected surface layer.

A new approach for semiconductor processing is described in which a melt is created at a semiconductor-metal (S-M) interface by shining light of a suitable spectrum from the semiconductor side. The melt can be controlled and confined to a thin region in the vicinity of the interface by controlling the energy delivered to the interface. The interface region regrows epitaxially on silicon as a Si-metal alloy. This phenomenon appears to be an optically induced effect. The interface reaction is greatly diminished if the light is incident from the metal side. This effect is applied to form low resistivity contacts to N+/ P type solar cells in a one-step process.

A new technique for improving the diffusion barrier properties of thin, thermallyevaporated nickel, chromium and nichrome films on silicon is described. In this technique, known as “Rapid Thermal Annealing” (RTA), profound differences in the diffusion barrier properties of the films annealed in ammonia ambient at 550-750°C, in comparison to films annealed only in vacuum, were observed. The films annealed in ammonia retained their integrity while the films annealed in vacuum showed diffusion of the silicon into the metal overlayer throughout the entire thickness of the metal in some cases. The film sheet resistance increase for the latter was consistent with the formation of the metal silicide. The possibility of extending this technique to electroplated films used in integrated and hybrid device fabrication is being studied.

A robust 6" hotwall flatzone nitride system is developed for scaled ONO interpoly. dielectric application in a high density EPROM memory cell. This system is designed to operate at low temperature (660° C) and gas ratio (4:1 NH3: DCS) with integrated silicon carbide components. The obtained key features are low defects (0.25 #/cm2 particles), smooth topography (measured by atomic force microscopy) and superior electrical interface as measured by electrical and optical methods.

In this work, we studied the rapid crystallization and the rapid tbermal oxidation of amorphous silicon films deposited at 465°C by low-pressure chemical vapor deposition (LPCVD) from disilane. The crystallization is well-controlled and the thermal bugdet is reduced compared to conventional processes. Results concerning the electrical and structural characteristics of poly-Si thin film transistors (TF7) are given. Furthermore, we obtained after plasma hydrogenation better mobilities in the case of rapid thermal processing (RTP) (μp-61 cm2/V.s, VT−8.3 V, subtbreshold slope−-0.8 V/decade, ION/IOFF− 1. 106 for p-type and μn-80 cm2/V.s, VT−3. 7 V, subthreshold slope−1.4 VWdecade, ION/IOFF−5.104 for n-type) compared to conventional processing performed at 600°C. The mobilities are improved by a factor of 2 to 3 despite the smaller grain size in the silicon films. We also showed a correlation between the optical absorption coefficient k (at 405nm) and the mobility wbicb appears not only dependent upon, the grain size but also upon the grain quality (grain boundaries and defects inside the grain).

This study shows that the structural and electrical properties of thin-films and oxides fabricated by RTP are at least as good as those obtained by conventional techniques.

The advantages of rapid thermal processing over slow, batch type processing have been demonstrated clearly in flat panel display manufacturing for a number of years. In the case of electroluminescence FPD, the brightness of the blue phosphor is increased by as much as 100%.

However, rapid thermal processors that use a lamp-based heat source - either a tungsten lamp array or a single arc lamp - have great difficulty in achieving heating uniformity over large areas.

By using a resistance-heated continuous heat source developed initially for RTP processing of large silicon wafers, temperature uniformity of less than +/− 2.5°C has been achieved over a panel with diagonal of 530mm.

A description of the system and its characteristics are presented.

Various ultrathin gate and capacitor structures were formed in a single wafer, lamp heated, reduced pressure, cold wall CVD reactor. Sequential processes including in-situ rapid thermal cleaning, surface passivation, and dielectric formation for capacitor structures was achieved at reduced pressure using pure ammonia. Three types of dielectric films were fabricated: pure thermal oxide, oxynitride, and silicon nitride. The films were grown using pure dry oxygen, nitrous oxide, and silane/ammonia chemistries, respectively. Excellent uniformity across the wafer was observed for dielectric films of different thicknesses. The RTCVD-based films exhibited improved characteristics for leakage and device drive. The TDDB data indicates that the short and long term reliability of the gate and capacitor dielectric films formed with the singlewafer process was better than that obtained with furnace-grown films. Auger electron spectroscopy and ellipsometry techniques were used to correlate film composition with processing conditions. In this paper we present the growth kinetics, composition, and thickness uniformity data and the electrical results of single-wafer processing.

A multiprocess CVD system with the following main features is designed and constructed: the wafer holder is made of a Si wafer with diameter larger than the process wafers. This larger holder produces a better temperature uniformity on the process wafer. A good thermal contact between holder and process wafer is obtained by an electrostatic clamp. The holder supports the process wafer facing down. A remote plasma is produced in a small chamber inside the process chamber. The 100 KHz RF frequency keeps the system very simple and cheap while still reasonable ionization is achieved. SiO2 films were deposited using SiH4 and O2 with and without remote plasma of O2. At low temperatures and 1.5 Torr, process activation energies of about 0.9 and 0.3 eV were obtained respectively.

The results of measurements of the physical properties of the dielectric grown on various orientations and surface doping concentration on silicon in an N2O environment are presented. We use this data to produce a model that predicts the dielectric thickness as a function of time and temperature.

In this paper both the substrate doping concentration and single crystal silicon orientation are considered when dielectrics are grown on silicon in a nitrous oxide environment. Our initial preliminary findings show that for heavily doped subtrates thicker layers of dielectric result compared to their lower doped counterparts. Furthermore we find a crossover point of temperature for growth rate for <111> compared to <100>. We believe that the different growth rates are attributable to nitrogen build up at the dielectric interface.