Although the benefits of in-situ processing seem intuitively obvious as higher yield due to particle and contamination control, there is presently little data to support these claims. However, materials characterization data on in-situ grown films suggest that it will be advantageous. In this paper we explore the advantages of in-situ processing in a load-locked rapid thermal chemical vapor deposition (RTCVD) chamber for such processes as cleaning, epitaxial growth, oxidation and polysilicon growth. The cold wall nature and low thermal mass of the RTCVD chamber make it an ideal candidate for a cluster module for thermal processing in an integrated process tool.

The effect of the average grading rate and of the number of incremental Ge alloy steps on the threading dislocation density has been studied in 30% Ge relaxed films formed by rapid thermal chemical vapor deposition (RTCVD) on Si substrates. Electron beam induced current (EBIC) images and transmission electron microscopy (TEM) show that threading defects fall in two categories: individual threading dislocations (dark spot defects), and organized clusters of these threads (pile-ups, or dark line defects). The overall surface defect density must include both categories to properly characterize the material. The lowest defect density, 4 × 105cm−2, was found in specimens grown at an average grading rate of 10% Ge per pm thickness.

Rapid Thermal Chemical Vapor Deposition (RTCVD) is a promising technology for thin film deposition in advanced cluster tool systems. It is well known that, if left uncompensated, excessive heat losses that occur around the wafer edge can lead to temperature and deposition non-uniformities. Using polysilicon deposition on SiO2 as an example we have shown that deposition non-uniformity can be aggravated by absorptivity variations across the wafer. In this paper, we propose a novel approach to alleviate this problem. In this technique, the edge cooling effect is compensated by increasing the absorptivity of the substrate around its perimeter. This is achieved by etching a thin (width≈200μm) ring from the isolation oxide around the wafer perimeter prior to polysilicon deposition. During polysilicon deposition, the absorptivity of the silicon-oxide-polysilicon structure continually changes resulting in positive and negative feedback mechanisms in certain polysilicon thickness ranges determined by both modeling and experiments. However, this absorptivity always remains less than the constant absorptivity of the silicon-polysilicon ring along the perimeter which is referred to here as the Constant Absorptivity Ring (CAR). The higher absorptivity of CAR shields edge cooling effects from the rest of the wafer. In this paper, we present the results of our experiments conducted to demonstrate the effectiveness of CAR in improving uniformity of polysilicon. We show that by using CAR uniform films can be obtained in a reactor which otherwise delivers a polysilicon non-uniformity of 30-40%.

In this paper, we report epitaxial growth of silicon in an ultra high vacuum rapid thermal chemical vapor deposition (UHV/RTCVD) equipment. In this study, our objectives were low temperature/low thermal budget processing and a high throughput compatible with single wafer manufacturing. The reactor consists of a load lock, a main process chamber and an intermediate cryopumped vacuum buffer chamber between the two chambers. An ultra-clean process environment was achieved using oil free pumps and point of use gas purifiers. The wafer is heated by a Peak Systems LXU-35 arc lamp through a quartz window. In this system, we achieved good quality silicon epitaxy at low temperature (T≤800°C) in the very low, 100 mTorr, pressure regime with high throughput (Growth rate>0.25 μm/min.). High growth rate was achieved using Si2H6 as the reactant gas instead of SiH4 or SiH2C12 which are more commonly used gases for epitaxial growth. High temperature in-situ cleaning was completely eliminated by initiating film growth on a hydrogen passivated surface obtained via dilute HF etching. Generation lifetimes in the 200-400μs range were measured for deposition temperatures of 700°C, 750°C and 800°C with no strong dependence on the deposition temperature.

Selectively deposited Si0.7Ge0.3 has been investigated as a potential diffusion source for fabricating ultra-shallow junctions in Si. Rapid thermal chemical vapor deposition (RTCVD) was used to selectively deposit Si0.7Ge0.3 on Si using SiH2C12, GeH4, and H2. Both ionimplanted and in-situ doped Si0.7Ge0.3 were considered as a diffusion source for fabricating ultra-shallow junctions. In-situ doping was achieved with B2H6 and PH3 for p-type and n-type doping, respectively. Boron and phosphorus diffusion in ion-implanted Si0.7Ge0.3 was investigated and modeled using SSUPREM4. Diffusion from implanted and in-situ doped Si0.7Ge0.3 in Si was also studied and modeled. Boron diffusivities in Si0.7Ge0.3 were found to be approximately 10 times greater than in Si, while phosphorus diffusivities were over 100 times greater in Si0.7Ge0.3. The faster dopant diffusivities in Si0.7Ge0.3 allow high surface concentration, abrupt diffusion profiles to be formed in Si. Gated, p-n junction diodes with junction depths as shallow as 140Å were fabricated and tested to study the quality of the diffusions from Si0.7Ge0.3.

In this paper, we report electrical characterization of raised source/drain MOS transistors fabricated using selectively deposited, in-situ boron doped SixGe1-x as a solid diffusion source to form the source/drain junctions. The alloy can be deposited with an enhanced selectivity at temperatures as low as 600°C resulting in an abrupt doping profile at the SixGe1-x/Si interface. After deposition, junctions are formed by diffusion of boron from the deposited layer into the silicon substrate. The selectively deposited alloy can serve as a sacrificial layer for self-aligned silicide formation elimintaing the problem of silicon consumption in the substrate. In this work, selective depositions were performed in a typical cold-walled, lamp heated rapid thermal chemical vapor deposition (RTCVD) system at ∼ 610 °C using SiH2C12, GeH4 and B2H6 as the reactive gases. Using this process, MOS transistors with effective channel lengths down to 0.45 gtm were successfully fabricated.

Thin silicon oxynitride (Si-O-N) films have been deposited using low pressure rapid thermal chemical vapor deposition (RTCVD) with silane (SiH4), nitrous oxide (N2O), and ammonia (NH3) as the reactive gases. Structural analysis coupled with a study of deposition conditions indicate that an increase in NH3/N2O flow rate ratios leads to an increased N/O atomic ratio and a decreased Si-O-N deposition rate. Thin film (55-75A) polySi/Si-N-O/Si capacitors and transistors were fabricated for NH3/N2O flow rate ratios from 20% to 100%. Some of the films were subjected to a post deposition anneal at 950°C for 15 seconds in both argon and oxygen. Capacitance voltage measurements indicate a mid-gap interface trap density of ≤ 6 × 1010 eV−1cm−2 for all the films independent of both nitrogen content and post deposition annealing conditions. The transconductance was studied as a function of NH3/N2O flow rate ratio and decreasing peak gm values but improved high field degradation was observed for increased nitrogen content. This is consistent with previous work on nitrided oxides and suggests that the films are under tensile stress. Hot carrier stress at maximum substrate current was performed with the Si-O-N films displaying larger threshold voltage shifts when compared to furnace SiO2 indicating the possible existence of hydrogen related traps.

PolySi films deposited with and without oxygen doping using rapid thermal chemical vapor deposition (RTCVD) have been investigated. Experimental results show that RTCVD systems can be used to provide high deposition rates ( 900-1000 Å/min at 700 °C) for both oxygen-doped and non-oxygen-doped polySi films. The surface roughness of the RTCVD polySi film is about half that of conventional LPCVD polySi films. The surface roughness and grain size of the RTCVD polySi film can be further reduced using oxygen doping. The catastrophic breakdown strength for capacitors using oxygen-doped polySi electrodes are improved compared with the breakdown strength for capacitors using non-oxygen-doped polySi electrodes. Electrical resistivities of B, P and As doped samples of polySi films with oxygen doping are found to be larger than those of polySi films without oxygen doping. Resistivities of silicides formed on the oxygen-doped polySi samples are approximately the same for those of silicides formed on non-oxygen-doped polySi samples.

Thermal stability of TiSi2 on blank, high–dose BF2+–, B+–, F+–, As+–, and P+–implanted silicon has been studied by both cross–sectional and plan–view transmission electron microscopy as well as by sheet resistance measurements. The surface morphology of TiSi2 was found to be significantly influenced by the implantation in silicon substrate.

Simultaneous presence of B and F was found to be most effective in stabilizing the TiSi2 thin films. Sheet resistance data were found to correlate well with the morphological and microstructural observation. The mechanisms for the stabilization of silicide films are discussed.

In VLSI technology, there is interest in monitoring the sequence of phase formation of TiSi2 (c-Ti ⇒ a-TiSi ⇒ C49 TiSi2 ⇒ C54 TiSi2), with the prospect of reducing the temperature of formation of the stable C54 TiSi2 phase. In this study, phase formation characteristics of TiSi2 during rapid thermal annealing(RTA) of Ti-Si bilayers are investigated by means of in situ four point probe resistance measurements. Ex situ X-ray diffraction(XRD) was used for phase identification and characterization. Results indicate that the same multi-step sequence of transformations precede the formation of the C54 TiSi2 phase for heating rates from 1°C/s to 100°C/s. Also, all intermediate and metastable phases which occur at l°C/s also occur at 100°C/s. Temperature dependence and kinetics of the C49 TiSi2 and the C54 TiSi2 phase formation were studied over a wide range of heating rates. Activation energies estimated for the two processes were ∼2eV and ∼5eV respectively. Finally, a new Electrical Thermal Annealing(ETA) technique for heating at rates up to 30000°C/s is introduced. Preliminary in situ resistivity measurement results of TiSi2 formation at these high heating rates are also presented.

We have extended our recent work on nano-scale CoSi2 formation from Co/Ti(O)multilayers on Si(100) to a self-aligned epitaxial CoSi2 structure produced by a two-step RTA annealing process. Parallel oxide stripes/Si windows were produced on a 4-inch Si(100) wafer by thermal oxidation and patterning. Six layers of 20nm Co and 10nm Ti were deposited sequentially on the patterned wafers with Ti as the first layer. The wafers were then annealed at 550°C to 700°C in N2 using a lamp RTA system. XTEM and RBS showed that a 25nm CoSi layer formed at the interface after a 650°C, 60sec annealing. The unreacted layers above it and oxide were selectively removed leaving a residual amorphous layer and CoSi intact on the patterned Si substrates. A second annealing at 900'C for 10sec produced 20nm of epitaxial CoSi2 covered with an ∼10nm CoxTiy(O)Siz surface layer. The epitaxial CoSi2 layer was thermally stable up to 1000°C, had a resistivity of ∼20μΩ-cm, and consumed ∼300Å of Si, thereby satisfying the most stringent deep submicron device contact scaling requirements.

Self aligned refractory metal silicides such as titanium disilicide have been used extensively in VLSI and ULSI structures. Unlike earlier work which has relied on undoped substrates and a single implant species, in the present study TiSi2 formation on phosphorous doped poly-Si in the presence of multiple dopants has been investigated. TEM micrographs are discussed which show the difference in silicide formation for the case of the BF2 and arsenic implanted samples. We have found that the presence of fluorine in the BF2 implant retards the silicide formation for phosphorous doped poly-Si substrates. Additionally, the effect of substrate grain size on TiSi2 formation has been investigated using undoped α-Si and poly-Si substrates.

The effects of heat treatment of polysilicon and amorphous Si films on their microstructure and thermal stability of polycides formed on these films have been studied. The number of grain boundaries decreases after pre-silicidation heat treatment in polysilicon due to grain growth but increases in amorphous Si due to nucleation. Since the thermal stability of CoSi2 polycide films was found to be closely related to the number of grain boundaries in the underlying silicon substrate, pre-silicidation heat treatments degrade the thermal stability of CoSi2 on as-deposited amorphous Si and improve the thermal stability of CoSi2 on asdeposited polysilicon. Doping does not have as pronounced an effects as substrate microstructure on CoSi21 polycide thermal stability, especially when dopants are introduced after silicidation by ion implantation.

Sputter deposited TiN films are commonly used as diffusion barriers for an aluminum based metallization and as glue layers for tungsten films in ULSI device processing. TiN is also used in conjunction with Ti and/or a-Si for local interconnect and salicide processing. For the above applications, TiN films are also subjected to rapid thermal processing.

This paper discusses these applications focusing on sub-half micron technologies where high aspect ratio contacts causes poor step coverage at the base of the contacts and compact design rule requirements pose an additional burden to Ti-silicide processes. Preferred grain orientation, microroughness, film stress, sheet resistance, diffusion barrier qualities and analytical spectroscopy techniques have been used to characterize the material modifications by RTP of Ti and Ti/TiN thin films.

In this work we studied titanium silicide formation by cosputtering onto silicon dioxide. Samples deposited with various (Si/Ti) atomic ratios were analyzed by Rutherford Backscattering Spectrometry (RBS). Isocronal annealings were conducted by means of Rapid Thermal Processing (RTP) in two types of furnaces: a vacuum and an atmospheric pressure (argon). Phase formation was monitored by resistivity measurements, X-Ray diffraction (XRD), and Scanning Electron Microscopy (SEM). It is observed that the final phase formation follows the thennodynamic equilibrium diagram, determined by stoichiometry, occurring at 800°C for the vacuum furnace, and at 900°C for the atmospheric RTP furnace. Sequential thermal treatments indicated the formation of TiSi2-C49 and/or TiSi after 400°C.

TiN diffusion barriers have been widely used in submicron contact structures, due to its good adhesion (to SiO2, W, Al and Si) properties, low diffusivity (for Si, W and Al) and compatibility with TiSi2 processing. The purpose of this paper is to present the results of physical and electrical characterization of contact structures with a TiN barrier and W plugs. Two different barrier metal processes were compared, Viz: sputtered Ti followed by post RTN and Ti/TiN films followed by post RTA in the range of 600° to 800°C. The devices were thermal stressed at 450°C for 7 hrs after W plug formation and Al metallization. Ti/TiN films with post RTA are generally superior barrier layers than Ti films with post RTA as shown by electrical characterization of contact resistance and barrier integrity. The relationship between electrical properties and microstructure for the two different barrier structures is discussed. W/TiN and TiN/TiSi2 interface structures were characterized using high resolution TEM. TiSi2 was found to be epitaxially grown during RTA, under certain process conditions. The crystal structure of TiSi2 was determined from electron diffraction patterns.

We report on a study of the effects of dopant concentration and linewidth on the formation of TiSi2 on polysilicon. The transformation from the C49 phase to the C54 phase is inhibited by a high concentration of either phosphorus or arsenic in blanket polysilicon films. For sub-half-micron lines, patterned in polysilicon doped with As or P, agglomeration is the key factor in the inability to produce low resistance silicide. The result is a critically shrinking process window for the attainment of low resistance VLSI interconnects.

A non-contact temperature measurement technique based on diffraction-analysis monitoring of the thermal expansion of materials is discussed. Due to the need for noncontact temperature measurements during semiconductor processing, silicon was chosen for this demonstration. The diffraction method requires a grating of suitable spatial frequency etched on the surface of the silicon wafer. The diffraction angle from the grating depends on the grating period which varies with temperature. Two symmetrically disposed incident beams are used to provide a differential measurement which is relatively independent of sample tilt. A computer system is used to monitor the diffraction order movement, from the order separation a relative temperature change can be calculated in near real-time. Temperature sensitivity for the diffraction technique is inversely dependent on the grating length (number of lines) and independent of the grating width. A sensitivity of 0.75°C is demonstrated for a 3-mm wide grating over a 20-700°C temperature range.

A new method of temperature control for rapid thermal processing of silicon wafers is presented whereby in-situ wafer temperature is determined by measurement of wafer thermal expansion via an optical micrometer mechanism. The expansion measurement technique and its implementation into a rapid thermal processing system for temperature control are described. Preliminary data show the wafer to wafer temperature repeatability to be 1% (3-σ) using this technique.

A new technique utilizing the high sensitivity of acoustic wave velocity to temperature is used to measure the wafer temperature in RTP. Acoustic energy is coupled to a Lamb wave mode in the wafer using the quartz support pins already present in most rapid thermal processors. The tips of the pins are sharpened to have point contact with the wafer and acoustic transducers are bonded to the other end to excite and detect acoustic waves. By measuring the pin-to-pin time of flight of Lamb waves, it is possible to monitor the wafer temperature in-situ in the 20 - 1000°C range with ±5°C accuracy. Increasing SNR to 50dB by spring loading the pins and using better electronics, it is possible to improve this figure to ±1°C. Also a modified system with multiple spring loaded pins is constructed and wafer temperature mapping is performed using tomographic reconstruction techniques. The resulting images are in good agreement with thermocouple readings and can be used for temperature control and rapid thermal processor design.