Distinct features of amorphous and polycrystalline silicon are attractive for large-area electronics. These features can be utilized in a hybrid structure which consists of both amorphous and polycrystalline silicon materials. For example, an extension of active matrix technology is the integration of peripheral drivers for the improvement of reliability, cost reduction and compactness of the packaging for large-area electronics. This goal can be approached by a combination of amorphous silicon pixel switches and polysilicon drivers. A monolithic fabrication process has been developed based on a simple modification of the amorphous silicon transistor process which uses selective area laser crystallization. This approach allows us to share many of the process steps involved in making both the amorphous and polysilicon devices. Another example of the hybrid device structure is a self-aligned amorphous silicon thin film transistor with polysilicon source and drain contacts. The advantages of the self-aligned transistor are reduction of the parasitic capacitance and scaling down of the device dimension. With a selective laser doping technique, self-aligned and short-channel amorphous silicon thin film transistors have been demonstrated.

We report the first amorphous silicon thin film transistors (TFTs) on flexible, ultra-thin substrates of 25 µm thick stainless steel foil. The transistors remain operational under convex or concave bending down to 2.5 mm radius of curvature. Taking advantage of the flexibility and resiliency of these devices, we have successfully fabricated TFTs using only xerographic toner masks printed directly on to the steel substrate and using mechanical alignment in the laser printer to obtain the necessary overlay accuracy. The goal of our work is to develop a foldable active-matrix transistor backplane, at low cost and high throughput, for use in highly rugged and portable applications such as foldable intelligent maps. Our results suggest that such foldable backplane circuits are feasible.

This article presents mechanisms for low temperature (<150°C) rf plasma enhanced chemical vapor deposition of silicon and silicon nitride thin films that lead to sufficient electronic quality for thin film transistor (TFT) fabrication and operation. For silicon deposition, hydrogen abstraction and etching, and silicon disproportionation reactions are identified that can lead to optimized hydrogen concentration and bonding environments at <150°C. Nitrogen dilution of SiH4/NH3 mixtures during silicon nitride deposition at low temperatures helps promote N-H bonding, leading to reduced charge trapping. Good quality amorphous silicon TFT's fabricated with a maximum processing temperature of 110 °C are demonstrated on flexible transparent plastic substrates. Transistors formed with the same process on glass and plastic show linear mobilities of 0.33 and 0.12 cm2/Vs, respectively, with ION/IOFF ratios > 106.

For the first time, we report a new poly-Si stepped gate Thin Film Transistor (SG TFT) on glass. The Density of States extracted from measured I-V characteristics has been used to evaluate the device performance with a two dimensional device simulator. The results show that the three-terminal SG TFT device has a switching speed comparable to a low voltage structure and the high on-current capability of a metal field plate (MFP) TFT and the potential for comparable breakdown characteristics.

In order to obtain stable thin-film silicon devices we are conducting research on the implementation of hot-wire CVD amorphous and polycrystalline silicon in thin-film transistors, TFTs. We present results on TFTs with a profiled active layer (deposited at ≥9 Å/s), and correlate the electrical properties with the structure of the silicon matrix at the insulator/semiconductor interface, as determined with cross-sectional transmission electron microscopy. Devices prepared with an appropriate H2 dilution of SiH4 show cone-shaped crystalline inclusions. These crystals start at the interface in some cases, and in others exhibit an 80nm incubation layer prior to nucleation. The crystals in the TFrs with the incubation layer are not cone-shaped, but are rounded off. The hot-wire CVD deposited devices exhibit a high field-effect mobility up to 1.5 cm2V−1s−1. Also, these devices have superior stability upon continuous gate bias stress, as compared to conventional glow-discharge a-Si:H TFTs. We ascribe this to a combination of enhanced structural order of the silicon and a low hydrogen content.

Amorphous silicon based thin film transistor liquid crystal displays (TFT/LCD) have become the dominant technology used for flat panel displays for notebook computers. The need for higher resolution, larger diagonal displays for both notebook and desktop applications is discussed. Calculations have shown that the use of high conductivity gate metal such as aluminum or copper, together with the implementation of improved groundrules, can significantly extend today's technology. Aluminum suffers from problems with hillock formation during PECVD processing, and copper typically has poor adhesion to glass, reaction problems with silicon and other PECVD films, and difficulties in contacting it to other metals. Approaches to solving problems with both materials are presented, and a novel reduced mask process to fabricate high resolution, high aperture ratio 10.5” SXGA (1280 × 1024) displays is described. The process uses copper gate metallurgy with redundancy, without the need for extra processing steps. The resulting displays have 150 dpi color resolution, an aperture ratio of over 35%, and excellent image quality, making them the first high resolution displays that are suitable for notebook applications.

Since being introduced to the production line in 1996, replacing the first generation a-Si TFT line, low-temperature poly-Si production technology aimed at manufacturing small and medium size LCD products has improved steadily corresponding to customers' requirements for rapid growth of the DVC and DSC markets. In the future, this production technology must progress to actual industry technology levels in order to cope with production applied not only to large size displays, which have a major market share in the present display market, but also to a large glass substrate, which effectively cuts the cost of products, although improvement of production yield and productivity in terms of pursuing cost reduction must be proceeded.

This paper has described existing problems of inherent low-temperature poly-Si TFT processes and their relating additional processes in present production methods. We have also discussed updating production technologies. To cope with production for a large size display, it is necessary to establish fabrication technology of higher performance TFTs with electron mobility larger than 200cm2/V s. We believe that one key technology is to fabricate a large-scale and highly-uniform recrystallized poly-Si film with smooth surface morphology as well as precisely-controlled grain size in production. To cope with production using a large glass substrate, it is essential to develop ELA equipment with laser power greater than 200W.

Using an approach we call “grain engineering,” we discuss several techniques to control grain growth during excimer laser annealing, to create low-defect density polysilicon films. By adjusting of laser parameters, for example, we obtain polysilicon films with grain sizes of more than 9 µm, without substrate heating. These high-quality films are used in the fabrication of low-temperature unhydrogenated polysilicon thin-film transistors (TFT's) yielding mobilities of > 260 cm2/Vs and on/off current ratios > 107. We investigate the laser recrystallization of “prepatterned” films as another technique of grain engineering. We find the performance of TFT's fabricated in active areas that are prepatterned before laser recrystallization is dramatically improved compared to those TFT's fabricated from the laser recrystallization of blanket polysilicon films. A novel “recessed” structure is also examined as a new grain engineering tool. By depositing a blanket silicon film on a patterned oxide layer on a heat sink, the heat flow through the continuous silicon film may be controlled during laser recrystallization to simultaneously produce adjacent regions of remarkably different grain microstructure.

In this work we have co-optimized the deposition and excimer laser crystallization processes for formation of high quality, low-temperature, p-Si films (LPS). We have found that the post-ELA polysilicon structure is very sensitive to deposition process adjustments, collectively expressed by the deposition rate. At low rates the PECVD Si-film is deposited in the microcrystalline phase (µc-Si). Comparing µc-Si and a-Si film precursors, we have shown that at equivalent annealing conditions (laser energy density) polysilicon films obtained from µc-Si precursor demonstrate improved crystallinity (grain size, defect density). Polysilicon thin film transistors (p-Si TFTs) have been fabricated and characterized using this material and compared to our standard process. We have found that the performance of µc-Si precursor exceeds by 20-50% that of a-Si precursor. Use of µc-Si precursor may also have important implications in reducing substrate damage during ELA process and for widening the ELA process window.

We have fabricated high-performance amorphous silicon thin-film transistors (a-Si:H TFTs) on 2 mil. (51 µm) thick polyimide foil substrates. The TFT structure was deposited by r.f.-excited plasma enhanced chemical vapor deposition (PECVD). All TFT layers, including the gate silicon nitride, the undoped, and the n+ amorphous silicon were deposited at a substrate temperature of 150°C. The transistors have inverted-staggered back-channel etch structure. The TFT off-current is ∼ 10−12 A, the on-off current ratio is > 107, the threshold voltage is 3.5 V, the sub-threshold slope is ∼ 0.5V/decade, and the linear-regime mobility is ∼ 0.5 cm2V−1s−1. We compare the mechanical behavior of a thin film on a stiff and on a compliant substrate. The thin film stress can be reduced to one half by changing from a stiff to a compliant substrate. A new equation is developed for the radius of curvature of thin films on compliant substrates.

Electrical test structures provide a method of rapid and low cost end-of-process metrology for both materials properties and specific process information. We have demonstrated the use of electrical test structures for monitoring key process parameters such as line width, edge taper width, layer-to-layer alignment, and data metal coverage over topography. These results are compared with those from traditional metrology methods and in all cases, the correlation was good, demonstrating that electrical test structures have sufficient accuracy for process control applications. For the structures used, the line width, edge taper width, and layer-to-layer alignment electrical measurements have uncertainties of less than 0.1 micron. A novel capacitance method was used for layer-to-layer alignment measurements and a combination of resistive and capacitive line width measurements were used to electrically determine the gate metal taper width. The test structures are all compatible with typical thin film transistor array processing.

A comparison of ion-implanted deuterium and ion implanted hydrogen for passivation of grain boundary states in poly-Si thin film transistors (TFTs) is presented for the first time. Gate-drain bias stressing was carried out after anneals at 350 °C, 400 °C, and 450 °C. Under stress, deuterated TFTs are more resistant to bias stress than hydrogenated TFTs in terms of most PMOS performance parameters and NMOS leakage current, but are markedly less resistant to NMOS threshold degradation. While still showing promise, these results are not as impressive as those shown for hot carrier degradation in very large scale integration (VLSI) MOS devices. After 350 °C activation anneal, deuterium is less effective than hydrogen at initial device passivation, probably as a result of excessive implant damage. After anneals at 400 or 450 °C, deuterium becomes more effective at passivation than hydrogen, possibly due to differences in diffusion between hydrogen and deuterium.

We report on the performance and hot carrier stress (HCS) reliability of n-channel poly-Si TFTs fabricated on bare or SiO2-coated low-alkali glass, or fused silica substrates. Low-pressure chemical vapor deposited (LPCVD) SiO2 films with different thicknesses are used as impurity diffusion barrier layers. We have found that the performance and HCS reliability of n-TFTs on the SiO2-coated glass are superior to those of n-TFTs on bare glass, and comparable to those of TFTs on fused silica. We also explore the impact of the SiO2 coating thickness on the performance and HCS reliability of the TFTs. The HCS reliability of the TFTs on SiO2-coated glass substrates is observed to depend on the SiO2 coating thickness. This is explained in terms of a phenomenological model which involves impurity and grain boundary traps.

We investigated the structure of hydrogenated amorphous silicon, thin films crystallized by short pulses from a XeCl excimer laser at fluences for which total melting of the films occurs. Atomic force microscopy revealed that films prepared using optimized process conditions, leading to hydrogen contents ≤ 5 at.%, are smoother after laser crystallization than those prepared by laser-dehydrogenation. The roughness of the laser-crystallized films increases with their thickness, and can be reduced by multiple exposure. A better smoothing is obtained by partially remelting the films after the first irradiation. Transmission electron microscopy shows that the grains in the laser-crystallized films have sizes that are comparable to the film thickness.

This work investigates the solid phase crystallization of PECVD amorphous silicon films by rapid thermal processing (RTP) as an alternative to laser crystallization. It is shown that PECVD films can be crystallized by RTP at temperatures compatible with glass substrates. A statistical design approach was used to investigate the effect of the various deposition and annealing conditions on the crystallization temperature, material properties and TFT device performance. The investigated variables include deposition temperature, rf power, pressure, surface treatments, dehydrogenation treatment, source gas, dilutant gas, and RTP scan speed. Important deposition and crystallization parameters will be discussed regarding polysilicon film optimization.

We propose a new method for selective crystallization of amorphous silicon and source/drain ion impurities activation by microwave annealing. We have measured FTIR to investigate hydrogen content variation in PECVD a-Si film and examined the poly-Si grain structure by SEM. We have also observed the Raman spectroscopy in order to investigate the grain growth mechanism during microwave annealing.

In our experiment, a-Si layer between microwave absorbing layers was fully crystallized in 60 seconds and hydrogen content of a-Si under microwave reflective layer was not varied after 20 minutes microwave annealing. These results indicate that proposed method may be implemented for fabricating a-Si and poly-Si TFTs on the same glass substrate. We have fabricated the poly-Si and a-Si TFTs employing microwave annealing for active layer crystallization and source/drain activation by our method.

Silicon dioxide thin films have been deposited at temperatures from 40°C to 250°C by plasma enhanced chemical vapor deposition (PECVD) using tetramethylsilane (TMS) as the silicon containing precursor. The properties of the PECVD TMS oxides (PETMS-Oxs) were analyzed with Fourier Transform Infrared (FTIR) transmission spectroscopy, BOE and P-etch rates and both current-voltage (I-V) and capacitance-voltage (C-V) electrical characterization. At both 130 °C and 250 °C, deposition conditions were identified which formed high quality as-deposited oxide films. Under the best conditions, unannealed Al/PETMS-Ox/c-Si capacitor structures displayed flat band voltages of Vfb = -2.5 V and breakdown fields (Vbd) in excess of 8 MV/cm. These PETMS-Ox films also show low leakage current densities <10-9 A/cm2 which can be maintained up to fields in excess of 4.5 MV/cm. The PETMS oxide electrical quality and process simplicity combine to make a very attractive oxide deposition technology for low temperature, large area applications.

In order to use a reflective FTIR measurement to evaluate thin films deposited on glass substrate, we have to consider several important factors, such as surface polarization, phase shift, and interference from different interfaces. PECVD thin films, oxide, nitride and a-Si:H deposited on top of the glass substrate are discussed by the reflective FTIR measurement.

Surface morphology and nucleation are important for forming electronic thin films on plastic substrates. We have used atomic force microscopy (AFM) with an oscillating cantilever to examine various transparent substrates, including 7059 glass, polyethylene terephthalate (PET), indium tin oxide (ITO)-coated PET, and polycarbonate, and studied the effect of deposition processes on these surfaces. Studies include: 1) differences in dielectric nucleation on plastics and glass; 2) dielectric growth evolution; and 3) the effect of plasma exposure on surface roughness. The surface morphology of the different substrate materials varied significantly with the PET showing the largest roughness values; all the polymers were more rough than typical 7059 glass (rms <0.5 nm). Furthermore, the initial nucleation on both polymers were different than on glass. Very thin layers (<30Å nominal thickness) of plasma deposited silicon nitride films on polycarbonate and glass produced flat, smooth surfaces, with rms roughness of ≈0.5 nm. On the PET substrates, the nitride growth began with broad, thin deposits and developed a coarse, large-grained structure as growth progressed. With exposure to a NH3 + N2 plasma, the glass and PET surfaces showed detectable changes in surface roughness, which are discussed below. These results demonstrate that plasma-deposited insulators nucleate and grow differently on plastic substrates than on glass, which has implications for electronic devices fabricated directly on plastics.