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Correlation of Performance and Hot Carrier Stress Reliability of Polycrystalline Silicon Thin-Film Transistors With Substrates and Substrate Coating

Published online by Cambridge University Press:  10 February 2011

Y. Z. Wang
Affiliation:
Electronic Materials and Processing Research LaboratoryThe Pennsylvania State University, University Park, PA 16802, [email protected]
O. O. Awadelkarim
Affiliation:
Electronic Materials and Processing Research LaboratoryThe Pennsylvania State University, University Park, PA 16802, [email protected]
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Abstract

We report on the performance and hot carrier stress (HCS) reliability of n-channel poly-Si TFTs fabricated on bare or SiO2-coated low-alkali glass, or fused silica substrates. Low-pressure chemical vapor deposited (LPCVD) SiO2 films with different thicknesses are used as impurity diffusion barrier layers. We have found that the performance and HCS reliability of n-TFTs on the SiO2-coated glass are superior to those of n-TFTs on bare glass, and comparable to those of TFTs on fused silica. We also explore the impact of the SiO2 coating thickness on the performance and HCS reliability of the TFTs. The HCS reliability of the TFTs on SiO2-coated glass substrates is observed to depend on the SiO2 coating thickness. This is explained in terms of a phenomenological model which involves impurity and grain boundary traps.

Type
Research Article
Copyright
Copyright © Materials Research Society 1998

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